SIMATIC PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP, Notas de estudo de Cultura

Baixe SIMATIC PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP e outras Notas de estudo em PDF para Cultura, somente na Docsity! Preface, Contents CPUs 1 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2 Cycle and Reaction times 3 CPU Function, depending on CPU and STEP 7 Version 4 Tips and Tricks 5 Appendix Standards, Certificates and Approvals A Dimensioned Drawings B List of Abbreviations C Glossary, Index Edition 10/2001 A5E00111190-01 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP Reference Manual SIMATIC This manual is part of the documentation package with the order number 6ES7398-8FA10-8BA0 Index-2 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 ! Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken. ! Warning indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken. ! Caution indicates that minor personal injury can result if proper precautions are not taken. Caution indicates that property damage can result if proper precautions are not taken. Notice draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation. Qualified Personnel Only qualified personnel should be allowed to install and work on this equipment. Qualified persons are defined as persons who are authorized to commission, to ground and to tag circuits, equipment, and systems in accordance with established safety practices and standards. Correct Usage Note the following: ! Warning This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended. Trademarks SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners. Safety Guidelines This manual contains notices intended to ensure personal safety, as well as to protect the products and connected equipment against damage. These notices are highlighted by the symbols shown below and graded according to severity by the following texts: We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed. Disclai of LiabilityCopyright
Siemens AG 2001 All rights reserved The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG Bereich Automatisierungs- und Antriebstechnik Geschaeftsgebiet Industrie-Automatisierungssysteme Postfach 4848, D- 90327 Nuernberg  Siemens AG 2001 Technical data subject to change. Siemens Aktiengesellschaft A5E00111190 Preface v PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Approbation, Standards and Approvals The SIMATIC S7-300 series conforms to:  Requirements and criteria to IEC 61131, Part 2  CE labeling – EC Guideline 73/23/EEC on Low Voltages – EC Guideline 89/336/EEC on electromagnetic compatibility (EMC)  Canadian Standards Association: CSA C22.2 Number 142, tested (Process Control Equipment)  Underwriters Laboratories, Inc.: UL 508 registered (Industrial Control Equipment)  Underwriters Laboratories, Inc.: UL 508 (Industrial Control Equipment)  Factory Mutual Research: Approval Standard Class Number 3611  C-Tick Australia Preface vi PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Integration in the Information Technology Environment This Manual forms part of the S7-300 documentation package: Reference Manual “CPU Data” CPU Data of CPU 312 IFM to 318-2 DP CPU Data of CPU 312C to 314C-2 PtP/DP “Technological Functions” Manual Manual Samples Installation Manual Manual Reference Manual “Module Data” Manual Operations List “CPU 312 IFM, 314 IFM, 313, 315, 315-2 DP, 316-2 DP, 318-2 DP” “CPUs 312C to 314C-2 PtP/DP Getting Started “S7-300” Description on how to operate, of the functions and of technical data of the CPU Description of specific technological functions:  Positioning  Counting  Point-to-point connection  Rules The CD contains examples of technological functions Description of how to create a project and how to install, wire, network and commission an S7-300 Description and technological details of signal modules, power supply modules and interface modules List of the CPU’s system resources and their execution times. Listing of all runtime function blocks (OBs/SFCs/SFBs) and their execution times the various Getting Started manuals offer help for commissioning your applications “CPU 31xC:Positioning with Analog Output” “CPU 31xC: Positioning with Digital Outputs” “CPU 31xC: Counting” “CPU 31xC: Point-to-point Communication “CPU 31xC: Controlling” “CPU 31xC: Y ou a re r ea di ng th is m an ua l Figure 1-1 S7-300, information technology environment Preface vii PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Complementary to this documentation package you require the following manuals: Manual “Integrated Functions CPU 312 IFM/314 IFM” Manual Order no.: 6ES7398-8CA00-8BA0 Reference Manual “System Software for S7-300/400 System and Standard Functions” Reference manual Part of the STEP 7 documentation package, order no. 6ES7810-4CA05-8BR0 Description of technological functions of the CPUs 312 IFM/314 IFM. Description of the SFCs, SFBs and OBs of the CPUs. This description is also available in the STEP 7 Online Help. Figure 1-2 Additional Documentation Further Support Please contact your local Siemens representative if you have any queries about the products described in this manual. http://www.ad.siemens.de/partner Training Center Newcomers to SIMATIC S7 PLCs are welcome to take part in our respective training courses. Please contact your local Training Center, or the central Training Center in D-90327 Nuremberg, Germany: Phone: +49 (911) 895-3200. http://www.sitrain.com Preface x PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 xi PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Contents 1 CPUs 1.1 Control and Display Elements 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Status and Fault Displays 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Mode Selector Switch 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Backup battery/accumulator 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 Memory card 1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.5 MPI and PROFIBUS-DP Interface 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.6 Clock and Runtime Meter 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Communication Options of the CPU 1-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Test Functions and Diagnostics 1-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Testing Functions 1-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Diagnostics with LED Display 1-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Diagnostics with STEP 7 1-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 CPUs - Technical Specifications 1-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 CPU 312 IFM 1-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 CPU 313 1-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 CPU 314 1-40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 CPU 314IFM 1-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 CPU 315 1-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.6 CPU 315-2 DP 1-63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.7 CPU 316-2 DP 1-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.8 CPU 318-2 1-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.1 Information on DPV1 Functionality 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 DP Address Areas of the CPUs 31x-2 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 CPU 31x-2 as DP Master 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Diagnostics of the CPU 31x-2 as DP Master 2-6 . . . . . . . . . . . . . . . . . . . . . . . . 2.5 CPU 31x-2 as DP-Slave 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents xii PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 2.6 Diagnosis of the CPU 31x-2 operating as DP-Slave 2-18 . . . . . . . . . . . . . . . . . . 2.6.1 Diagnosis with LEDs 2-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Diagnostics with STEP 5 or STEP 7 2-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Reading Out the Diagnostic Data 2-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4 Format of the Slave Diagnostic Data 2-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.5 Station Status 1 to 3 2-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.6 Master PROFIBUS Address 2-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7 Manufacturer ID 2-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.8 Module Diagnostics 2-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.9 Station Diagnostics 2-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.10 Interrupts 2-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Direct Data Exchange 2-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Diagnosis with Direct Communication 2-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Cycle and Reaction times 3.1 Cycle time 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Response Time 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Calculation Examples for Cycle Time and Response Time 3-10 . . . . . . . . . . . . 3.4 Interrupt response time 3-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Calculation Example for the Interrupt Response Time 3-16 . . . . . . . . . . . . . . . . 3.6 Reproducibility of Delay and Watchdog Interrupts 3-16 . . . . . . . . . . . . . . . . . . . . 4 CPU Function, depending on CPU and STEP 7 Version 4.1 Differences between CPU 3182 and CPUs 312 IFM to 3162 DP 4-2 . . . . . . . 4.2 The Differences Between the CPUs 312 IFM to 318 and Their Previous Versions 4-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Tips and Tricks A Standards, Certificates and Approvals B Dimensioned Drawings C List of Abbreviations Glossary Index 1-1 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 CPUs In This Section Section Contents Page 1.1 Control and Display Elements 1-2 1.2 CPU Communication Options 1-11 1.3 Test Functions and Diagnostics 1-19 1.4 CPUs - Technical Specifications 1-24 Agreement for CPU 314IFM The CPU 314IFM is available in 2 versions:  with slot for memory card (6ES7314-5EA10-0AB0)  without slot for memory card (6ES7314-5EA0x-0AB0/ 6314ES7314-5EA8x-0AB0) All details in this chapter apply to both versions of the CPU314IFM unless explicit reference is made to differences between them. 1 CPUs 1-2 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.1 Control and Display Elements Figure 1-1 shows you the control and display elements of a CPU. The order of the elements in some CPUs might differ from the order shown in the figure below. The individual CPUs do not always have all the elements shown here. Table 1-1 shows you the differences. Slot for memory card Compartment for backup battery or rechargeable battery M L +M PROFIBUS-DP interface Status and fault LEDs Mode selector Connection for power supply and system ground Multipoint Interface (MPI) Status and fault displays for DP interface Figure 1-1 Control and Display Elements of the CPUs Differences Between CPUs Table 1-1 The Differences in Control and Display Elements Between CPUs Element 312 IFM 313 314 314 IFM 315 315-2 316-2 318-2 -5AE0x - -5AE10 - DP DP LEDs for DP interface No Yes Backup battery/accumulator No No accumu- lator Yes Connection for power supply No; via the front connector Yes Memory card No Yes No Yes Yes PROFIBUS-DP interface No Yes CPUs 1-3 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.1.1 Status and Fault Displays SF ... (red) ...hardware/software error BATF ... (red) ...battery error (not CPU 312 IFM) DC5V ... (green) ... 5V DC supply for CPU and S7-300 bus is ok. FRCE ... (yellow) ...force job is active RUN ... (green) ... CPU in RUN mode; LED flashes at start-up with 1 Hz; in HALT mode with 0.5 Hz STOP ... (yellow) ... CPU in STOP/HALT or STARTUP mode; LED flashes on request to reset memory BUSF ... (red) ... hardware or software fault at PROFIBUS interfaceCPU 315-2 DP/ CPU 316-2 DP Displays for the CPU: Displays for the PROFIBUS: BUS2F ... (red) ... hardware or software fault at interface 2 BUS1F ... (red) ... hardware or software fault at interface 1CPU 318-2 Figure 1-2 Status and Fault Displays of the CPUs CPUs 1-6 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.1.4 Memory card Exceptions You cannot insert a memory card with the CPUs 312 IFM and 314 IFM (-5AE0x). These CPUs have an integrated read-only memory. Purpose of the Memory Card With the memory card, you can expand the load memory of your CPU. You can store the user program and the parameters that set the responses of the CPU and modules on the memory card. You can also back up your CPU operating system to a Memory Card. except CPU 318-2. If you store the user program on the memory card, it will remain in the CPU when the power is off even without a backup battery. Available Memory Cards The following memory cards are available: Table 1-3 Memory Cards Capacity Type Remarks 16 KB 32 KB The CPU supports the following functions:  64 KB Loading of the user program on the module into the CPU 256 KB With this function, the memory of the 128 KB 5 V FEPROM CPU is reset, the user program is 512 KB downloaded onto the memory card, and then uploaded from the memory card to 1 MB the CPU’s RAM.  2 MB Copying RAM data to ROM (not with CPU318-3182) 4 MB 128 KB 256 KB 512 KB 5 V RAM Only with the CPU 318-2 1 MB 2 MB CPUs 1-7 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.1.5 MPI and PROFIBUS-DP Interface Table 1-4 CPU Interfaces CPU 312 IFM CPU 313 CPU 314IFM CPU 314 CPU 315-2DP CPU 316-2DP CPU 318-2 MPI interface MPI interface PROFIBUS-DP interface MPI/DP Interface PROFIBUS-DP interface MPI MPI DP MPI/ DP DP - - - Reconfiguration as a PROFIBUS-DP interface is possible - MPI interface The MPI is the interface of the CPU for the programming device/OP and for communication in an MPI subnet. Typical (default) transmission speed is 187.5 Kbps (CPU 318-2: adjustable up to 12 Mbps). Communication with an S7-200 requires 19.2 Kbps. The CPU automatically broadcasts its set bus parameters (e.g. baud rate) at the MPI interface. This means that a programming device, for example, can automatically ”hook up” to an MPI subnet. PROFIBUS-DP Interface CPUs equipped with 2 interfaces provide a PROFIBUS-DP interface connection. Transmission rates up to 12 Mbps are possible. The CPU automatically broadcasts its set bus parameters (e.g. baud rate) at the PROFIBUS-DP interface. This means that a programming device, for example, can automatically ”hook up” to a PROFIBUS subnet. In Step 7 you can switch off automatic transfer of bus parameter. CPUs 1-8 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Connectable Devices MPI PROFIBUS-DP  Programming device/PC and OP  S7 programmable controller with MPI interface (S7-300, M7-300, S7-400, M7-400, C7-6xx)  S7-200 (Note: 19.2 Kbps only)  Programming device/PC and OP  S7 programmable controllers with the PROFIBUS-DP interface (S7-200, S7-300, M7-300, S7-400, M7-400, C7-6xx)  Other DP masters and DP slaves Only 19.2 Kbps for S7-200 in MPI Subnet Note At 19.2 Kbps for communicating with S7-200, – a maximum of 8 nodes (CPU, PD/OP, FM/CP with own MPI address) is permitted in a subnet, and – no global data communication can be carried out. Please consult the S7200 Manual for further information! Removing and Inserting Modules in the MPI Subnet You must not plug in or remove any modules (SM, FM, CP) of an S7-300 configuration while data is being transmitted over the MPI. ! Warning If you remove or plug in S7-300 modules (SM, FM, CP) during data transmission via the MPI, the data might be corrupted by disturbing pulses. You must not plug in or remove modules (SM, FM, CP) of an S7-300 configuration during data transmission via the MPI! CPUs 1-11 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Behavior of Clock in POWER OFF Mode The following table shows the clock behavior with the power of the CPU off, depending on the backup: Backup CPU 314 to 318-2 CPU 312 IFM and 313 With backup battery The clock continues to operate in power off mode. At POWER ON, the clock continues to operate using the clock time at which POWER OFF took place. With accumulator The clock continues to operate in power off mode for the backup time of the accumulator. When the power is on, the accumulator is recharged. Since the clock does not have a power buffer, it does not continue to run in POWER OFF mode. In the event of backup failure, an error message is not generated. When the power comes on again, the clock continues at the clock time at which the power went off. None At POWER ON, the clock continues to operate using the clock time at which POWER OFF took place. Since the CPU is not backed up, the clock does not continue at POWER OFF. 1.2 Communication Options of the CPU The CPUs offer you the following communication options: CPUs 1-12 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Table 1-6 CPU Communication Options Communications MPI DP Description PG/OP Communication x x A CPU can maintain several on-line connections simultaneously with one or more programming devices or operator panels. For PD/OP communication via the DP interface, you must activate the “Programming, modifying and monitoring via the PROFIBUS” function when configuring and assigning parameters to the CPU. S7 Basic Communication x x Using the I system functions, you can transfer data over the MPI/DP network within an S7-300 (acknowledged data exchange). Data exchange takes place via non-configured S7 connections. x - Using the XI system functions, you can transfer data to other communication peers in the MPI subnet (acknowledged data exchange). Data exchange takes place via non-configured S7 connections. A listing of I/X SFCs is found in the Instruction List. Details are found in the STEP 7 Online Help or in the System and Standard Functions reference manual. Routing of PG Functions x x With CPUs 31x-2 and STEP 7 as of V 5/0, you can route your PG/PC to S7 stations of other subnets, e.g. for downloading user programs or hardware configurations, or executing, testing and commissioning functions. Routing with the DP interface requires you to activate the “Programming, Status/Control...” function when configuring and assigning parameters to the CPU. Details on routing are found in the STEP 7-Online Help. S7 Communication x - S7 communication takes place via configured S7 connections. Here, the S7-300-CPUs are servers for S7-400 CPUs. That is, S7-400 CPUs have read/write access to S7-300 CPUs. Global Data Communication x - The CPUs of the S7-300/400 can exchange global data with one another (unacknowledged data exchange). CPUs 1-13 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Connection Resources Every communication connection requires a communication resource on the S7 CPU as a management unit for the duration of the communication. Every S7 CPU has a certain number of connection resources available to it according to its technical specifications which can be assigned to various communication services (PD/OP communication, S7 communication or S7 basic communication). The distribution of connection resources differs between CPUs 312 IFM to 316-2 DP (see the table 3-6) and the CPU 318-2 (see Table 1-8): CPUs 1-16 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Interface Resources for CPU 318-2 - Example Calculation 1. Two network transitions by routing on the CPU Resources used: - 2 connection resources of the MPI/DP interface are used; - 2 connection resources of the DP interface are used; - all 4 connection resources available to both interfaces are used; 2. 4 connections for S7 basic communication and PG/OP communication with the CPU as connection terminal point via MPI/DP interface Resources used: - 4 connection resources of the MPI/DP interface are used; - all 4 connection resources available to both interfaces are used; Resources still availabe: - 26 connection resources of the MPI/DP interface; - 14 connection resources of the DP interface; - 24 of the connection resources available to both interfaces Data Consistency for Communication An essential aspect of the transmission of data between devices is its consistency. The data that is transmitted together should all originate from the same processing cycle and should thus belong together, i.e. be consistent. If there is a programmed communication function such as X-SEND/ X-RCV which accesses shared data, then access to that data area can be co-ordinated by means of the parameter “BUSY” itself. However, with S7 communication functions not requiring a block in the user program of the 31x CPU (as server), e.g. PUT/GET or read/write operations via OP communication, the dimension of data consistency must be taken into account during programming. The following differences between CPUs 312IFM to 316-2 DP and CPU 318-2 must be taken into account: CPUs 1-17 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 CPU 312 IFM to 316-2 DP CPU 318-2 PUT/GET functions of S7 communication, or reading/writing variables via OP communication, are processed during the PUT/GET functions of S7 communication, or reading/writing to variable via OP communication are processed in defined time cycle checkpoint of the CPU. A defined process interrupt reaction time is ensured by consistent copying of communication variables in blocks of 32 bytes (CPU Versions lower than described in this windows in the CPU 318-2 operating system. For that reason, the user program can be interrupted after every command (Byte/Word/Double Word command) when a communication variable is being accessed. The data consistency of a communicationmanual: Blocks of up to 8 Bytes) into/out of user memory during the cycle checkpoint of the operating system. Data consistency is not guaranteed for any larger data areas. Therefore, communication variables in the variable is therefore only possible within the limits of the command boundaries used in the user program. If a data consistency size greater than Byte, user program must not exceed a length of 8 or 32 byte if data consistency is required. If you copy communication variables using SFC 81 “UBLKMOV”, the copying process is not interrupted by higher priority classes. Word or DWord is required, communication variables in the user program must always be copied using SFC81 “UBLKMOV” that guarantees consistent reading/writing of the complete communication variable area. CPUs 1-18 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Details ... on the communication topic are found in the STEP 7 Online Help and in the manual Communication with SIMATIC. ... on communications SFCs/SFBs are found in the STEP 7 Online Help and in the Standard and System functions reference manual. Global Data Communication with S7-300 CPUs Below you will find important features of global data communication in the S7-300. Send/Receive Conditions For the communication via GD circuits, you should observe the following conditions:  Required for the GD packet transmitter is: Reduction ratio Transmitter  Cycle time Transmitter  60 ms (CPU 318-2: 10 ms  Required for the GD packet receiver is: Reduction ratio Receiver  Cycle timer eceiver  Reduction ratio Transmitter  Cycle time Transmitter Non-observance of these conditions can lead to the loss of a GD packet. The reasons for this are:  The performance capability of the smallest CPU in the GD circuit  Sending and receiving of global data is carried out asynchronously by the sender and receiver. Loss of global data is displayed in the status field of a GD circuit if you have configured this with STEP 7. Note Note when communicating via global data: sent global data is not acknowledged by the receiving partner! The sender therefore receives no information on whether a receiver and which receiver has received the sent global data. Send Cycles for Global Data In STEP 7 (as of Version 3.0), the following situation can arise if you set “Send after every CPU cycle” with a short CPU cycle time (< 60 ms): the operating system overwrites GD packets the CPU has not yet transmitted. Tip: Loss of global data is displayed in the status field of a GD circuit if you have configured this with STEP 7. CPUs 1-21 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Forcing with the CPU 312 IFM to 316-2 DP: ! Caution Forced values in the input process image can be overwritten by write instructions (e.g. T EB x, = E x.y, copying with SFC etc.) and peripheral read instructions (e.g. L PEW x) in the user program, as well as by write instructions of PG/OP opera- tions! Outputs initialized with forced values only return the forced value if the user pro- gram does not execute any write accesses to the outputs using peripheral write commands (e.g. TPQB x ) and if no PG/OP functions write to these outputs! Always note that forced values in the I/O process image cannot be overwritten by the user program or PG/OP functions! Execute force job for outputs With S7-300 CPUs, forcing is the same as “cyclical modify” PII transfer User program OS T PQW Forced value overwritten by T PQW! Execute force job for inputs Forced value Execute force job for outputs Forced value Execute force job for inputs OS .... Operating system execution PIO transfer PII transfer OS PIO transfer Figure 1-4 The Principle of Forcing with S7-300 CPUs (CPU 312IFM to 316-2DP) CPUs 1-22 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.3.2 Diagnostics with LED Display In Table 1-9, only the LEDs relevant to the diagnosis of the CPU and S7-300 are listed. You will find the significance of the PROFIBUS-DP interface LEDs explained in Chapter 2. Table 1-9 Diagnostic LEDs of the CPU LED Description SF Comes on in the event of Hardware faults Programming errors Parameter assignment errors Calculation errors Timing errors Faulty memory card Battery fault or no backup at power on I/O fault/error (external I/O only) Communication error BATF Comes on when The backup battery is missing, faulty or not charged. Note Also lit if a rechargeable battery is installed. Reason: The user program is not backed up the rechargeable battery. Stop Comes on when Flashes when The CPU is not processing a user program The CPU requests a memory reset 1.3.3 Diagnostics with STEP 7 Note Please note that this is not a fail-safe or redundant system, regardless of its exi- sting extensive monitoring and error reaction functions. If an error occurs, the CPU enters the cause of the error in the diagnostic buffer. You can read the diagnostic buffer using the programming device. The CPU switches to STOP if an error or interrupt event occurs, or your user program reacts accordingly with error or interrupt OBs. Details on STEP 7 diagnostic functions are found in the STEP 7 Online Help. In the Instruction list you can find an overview  of the OBs you can use to react to respective error or interrupt events, as well  as of the OBs you can program in the respective CPU CPUs 1-23 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 CPU Reaction on Missing Error OB If you have not programmed an error OB, the CPU reacts as follows: CPU goes into STOP on missing ... CPU Remains in RUN with Missing ... OB 80 (Runtime error) OB 85 (Program cycle error) OB 86 (Station failure in the PROFIBUS- DP subnet) OB 87 (Communication error) OB 121 (Programming error) OB 122 (Peripheral direct access error) OB 81 (Power break) CPU Behavior When There Is No Interrupt OB If you have not programmed an interrupt OB, the CPU reacts as follows: CPU goes into STOP on missing ... CPU Remains in RUN with Missing ... OB 10/11 (TOD interrupt) OB 20/21 (Delay interrupt) OB 40/41 (Process interrupt) OB 55 (TOD interrupt) OB 56 (Delay interrupt) OB 57 (for manufacturer-specific interrupts) OB 82 (Diagnostic interrupt) OB 83 (Insertion/Removal interrupt) OB 32/35 (Watchdog interrupt) Tip on OB35 (CPU 318-2: also OB32) For the watchdog interrupt OB 35/32, you can specify times starting from 1 ms. Note: The smaller the selected watchdog interrupt period, the more likely watchdog interrupt errors will occur. You must take into account the operating system times of the CPU in question, the runtime of the user program and the extension of the cycle by active programming device functions, for example. CPUs 1-26 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Start information for OB40 Table 1-10 shows the temporary (TEMP) variables of OB40 relevant for the “Interrupt inputs” of the CPU 312 IFM. Refer to theSystem and Standard functions reference manual for details on the process interrupt OB. Table 1-10 Start Information for OB 40 for the Interrupt Inputs of the Integrated I/Os Byte Variable Data Type Description 6/7 OB40_MDL_ADDR WORD B#16#7C Address of the interrupt triggering module (in this case, the CPU) 8 on OB40_POINT_ADDR DWORD See Figure 1-5 Signaling of the interrupt triggering integrated inputs Display of the Interrupt Inputs In variable OB40_POINT_ADDR, you can view the interrupt inputs which have triggered a process interrupt. Figure 1-5 shows the allocation of the interrupt inputs to the bits of the double word. Note: Several bits can be set if interrupts are triggered by several inputs within short intervals (< 100
s). That is, the OB is started once only, even if several interrupts are pending. 0 Bit No. PRIN from I124.6 5 4 13 231 30 PRIN from I 124.7 PRIN from I125.0 PRIN from I 125.1 Reserved PRIN: Process interrupt Figure 1-5 Display of the States of the Interrupt Inputs of the CPU 312 IFM CPUs 1-27 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Front View Status and fault LEDs Mode selector Multipoint Interface (MPI) Front connector, used to connect the integrated I/O, power supply and system ground. I124.0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I125.0 I 1 Q124.0 Q 1 Q 3 Q 2 Q 4 Q 5 Figure 1-6 Front View of the CPU 312 IFM CPUs 1-28 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the CPU 312 IFM CPU and Product Version MLFB  Hardware version 6ES7 312-5AC02-0AB0 01  Firmware version V 1.1.0  Matching programming package STEP 7 V 5.0; Service Pack 03 Memory Work memory  integral 6 KB  Expandable no Load memory  integral 20 KB RAM 20 KB EEPROM  Expandable FEPROM no  Expandable RAM no Backup Yes  With battery no  Without battery 72 bytes retentive Configurable (data, flags, timers) Processing times Processing times for  Bit instructions 0.6
s minimum  Word instructions 2
s minimum  Double integer math 3
s minimum  Floating-point math instructions 60
s minimum Timers/Counters and their retentive characteristics S7 counters 32  Adjustable retentivity from C 0 to C 31  Preset from C 0 to C 7  Counting range 1 to 999 IEC Counters Yes  Type SFBs S7 timers 64  Adjustable retentivity No  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFBs Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) max. 1 DB, 72 data bytes Bit memories 1024  Adjustable retentivity MB 0 to MB 71  Preset MB 0 to MB 15 Clock memories 8 (1 memory byte) Data blocks max. 63 (DB 0 reserved)  Size max. 6 KB  Adjustable retentivity max. 1 DB, 72 bytes  Preset No retentivity Local data (non-alterable) max. 512 bytes  Per priority class 256 bytes Blocks OBs See Instruction List  Size max. 6 KB Nesting depth  Per priority class 8  additional levels within an error OB None FBs max. 32;  Size max. 6 KB FCs max. 32;  Size max. 6 KB Address areas (I/O) Peripheral address area  Digital – integrated 0 to 31/0 to 31 124,125 E/124 A  Analog 256 to 383/256 to 383 Process image (cannot be customized) 32 bytes+4 bytes integrated/ 32 bytes+4 bytes integrated Digital channels 256+10 integrated/256+6 integrated Analog channels 64/32 CPUs 1-31 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Special Inputs of the CPU 312IFM Module-Specific Data Number of inputs 4 I 124.6 to 125.1 Cable length  Shielded max. 100 m (109yd.) Voltages, Currents, Potentials Number of inputs that can be triggered simultaneously  (horizontal configuration) up to 60°C  (vertical configuration) up to 40°C 4 4 4 Status, Interrupts; Diagnostics Status display 1 green LED per channel Interrupts  Process interrupt Configurable Diagnostic functions None Sensor Selection Data Input voltage  Rated value  For “1” signal I 125.0 and I 125.1 I 124.6 and I 124.7  For “0” signal 24V DC 15 to 30 V 15 to 30 V -3 to 5 V Input current  For “1” signal I 125.0 and I 125.1 I 124.6 and I 124.7 min. 2 mA min. 6.5 mA Input delay time  For “0” to “1”  For “1” to “0” max. 50
s max. 50
s Input characteristic E 125.0 and E 125.1 E 124.6 and 124.7 to IEC 1131, Type 1 to IEC 1131, Type 1 Connection of 2-wire BEROs  Permissible idle current I 125.0 and I 125.1 I 124.6 and I 124.7 no max. 0.5 mA max. 2 mA Time, Frequency Internal conditioning time for  Interrupt processing max. 1.5 ms Input frequency  10 kHz CPUs 1-32 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Digital Inputs of the CPU 312IFM Note Alternatively, you can configure the inputs I 124.6 and I 124.7 as special inputs, in which case the technical specifications listed for the special inputs apply to the inputs I 124.6 and I 124.7. Module-Specific Data Number of inputs 8 Cable length  Unshielded  Shielded max. 600 m max. 1000 m Voltages, Currents, Potentials Number of inputs that can be triggered simultaneously  (horizontal configuration) up to 60°C  (vertical configuration) up to 40°C 8 8 8 Galvanic isolation No Status, Interrupts; Diagnostics Status display 1 green LED per channel Interrupts None Diagnostic functions None Sensor Selection Data Input voltage  Rated value  For “1” signal  For “0” signal 24V DC 11 to 30 V -3 to 5 V Input current  For “1” signal typical 7 mA Input delay time  For “0” to “1”  For “1” to “0” 1.2 to 4.8 ms 1.2 to 4.8 ms Input characteristic to IEC 1131, Type 2 Connection of 2-wire BEROs  Permissible quiescent current Possible max. 2 mA CPUs 1-33 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Digital Outputs of the CPU 312IFM Module-Specific Data Number of outputs 6 Cable length  Unshielded  Shielded max. 600 m max. 1000 m Voltages, Currents, Potentials Total current of outputs (per group)  (horizontal configuration) up to 40°C up to 60°C  (vertical configuration) up to 40°C max. 3 A max. 3 A max. 3 A Galvanic isolation No Status, Interrupts; Diagnostics Status display 1 green LED per channel Interrupts None Diagnostic functions None Actuator Selection Data Output voltage  For “1” signal min. L+ (-0.8 V) Output current  For “1” signal Rated value Permissible range  For “0” signal Residual current 0.5 A 5 mA to 0.6 A max. 0.5 mA Load impedance range 48  to 4 k Lamp load max. 5 W Parallel connection of 2 outputs  For dual-channel triggering of a load  For performance increase Possible Not possible Triggering of a digital input Possible Switching frequency  For resistive load  For inductive load to IEC947-5-1, DC 13  For lamp load max. 100 Hz max. 0.5 Hz max. 100 Hz Inductive breaking voltage limited internally to typical V 30 Short-circuit protection of the output  Response threshold yes, electronically timed typical 1 A CPUs 1-36 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Basic Circuit Diagram of the CPU 312 IFM Figure 1-8 shows the block diagram of CPU 312 IFM. CPU CPU power supply M L + M Figure 1-8 Basic Circuit Diagram of the CPU 312 IFM CPUs 1-37 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.4.2 CPU 313 Technical Specifications of the CPU 313 CPU and Product Version MLFB  Hardware version 6ES7 313-1AD03-0AB0 01  Firmware version V 1.1.0  Matching programming package STEP 7 V 5.0; Service Pack 03 Memory Work memory  integral 12 KB  Expandable no Load memory  integral 20 KB RAM  Expandable FEPROM Up to 4 MB  Expandable RAM no Backup Yes  With battery All data  Without battery 72 bytes retentive Configurable (data, flags, timers) Processing times Processing times for  Bit instructions 0.6
s minimum  Word instructions 2
s minimum  Double integer math 2
s minimum  Floating-point math instructions 60
s minimum Timers/Counters and their retentive characteristics S7 counters 64  Adjustable retentivity from C 0 to C 63  Preset from C 0 to C 7  Counting range 1 to 999 IEC Counters Yes  Type SFB S7 timers 128  Adjustable retentivity from T 0 to T 31  Preset No retentive times  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFB Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) max. 1 DB, 72 data bytes Bit memories 2048  Adjustable retentivity MB 0 to MB 71  Preset MB 0 to MB 15 Clock memories 8 (1 memory byte) Data blocks max. 127 (DB 0 reserved)  Size max. 8 KB  Adjustable retentivity 1 DB, 72 bytes  Preset No retentivity Local data (non-alterable) max. 1536 bytes  Per priority class 256 bytes Blocks OBs See Instruction List  Size max. 8 KB Nesting depth  Per priority class 8  additional levels within an error OB 4 FBs 128  Size max. 8 KB FCs 128  Size max. 8 KB Address areas (I/O) Peripheral address area  Digital 0 to 31/0 to 31  Analog 256 to 383/256 to 383 Process image (cannot be customized) 32 bytes/32 bytes Digital channels max. 256/256 Analog channels max. 64/32 CPUs 1-38 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Configuration Rack 1 Modules per module rack max. 8 Number of DP masters  integral No  via CP 1 S7 message functions Simultaneously active Alarm-S blocks None Time Real-time clock Yes  Backed-up No  Accuracy See Section 1.1.6 Operating hours counter 1  Number 0  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master  On MPI Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DBs, timers, counters  Number – Monitor Variables – Modify Variables max. 30 max. 14 Force Yes  Variable Inputs, outputs  Number max. 10 Monitor block Yes Single sequence Breakpoint Yes 2 Diagnostic buffer Yes  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 1  Size of GD packets max. 22 bytes – Number of which consistent 8 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 32 bytes for X/I_PUT/_GET; 76 bytes for X_SEND/_RCV S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent 32 bytes S7-compatible communication No Standard communication No Number of connection resources 8 for PD/OP/S7 basic/S7 communication  Reservation for – PD communication User-definable Default max. 7 from 1 to 7 1 – OP communication User-definable Default max. 7 from 1 to 7 1 – S7 basic communication User-definable Default max. 4 from 0 to 4 4 Interfaces 1. Interface Functionality  MPI Yes  DP Master No  DP Slave No  Galvanically isolated No CPUs 1-41 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Configuration Rack max. 4 Modules per module rack max. 8 Number of DP masters  integral None  via CP 1 S7 message functions Simultaneously active Alarm-S blocks max. 40 Time Real-time clock Yes  Backed-up Yes  Accuracy See Section 1.1.6 Operating hours counter 1  Number 0  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master  On MPI Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DBs, timers, counters  Number – Monitor Variables – Modify Variables max. 30 max. 14 Force Yes  Variable Inputs, outputs  Number max. 10 Monitor block Yes Single sequence Breakpoint Yes 2 Diagnostic buffer Yes  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 1  Size of GD packets max. 22 bytes – Number of which consistent 8 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 32 bytes for X/I_PUT/_GET; 76 bytes for X_SEND/_RCV S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent 32 bytes S7-compatible communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Standard communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Number of connection resources 12 for PD/OP/S7 basic/S7 communication  Reservation for – PD communication User-definable Default max. 11 from 1 to 11 1 – OP communication User-definable Default max. 11 from 1 to 11 1 – S7 basic communication User-definable Default max. 8 from 0 to 8 8 Interfaces 1. Interface Functionality  MPI Yes  DP Master No  DP Slave No  Galvanically isolated No CPUs 1-42 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 MPI  Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server)  Transmission rates 19.2; 187.5 Kbps Dimensions Assembly dimension BHT (mm) 80125130 Weight Approx. 0.53 kg Programming Programming language STEP 7 Stored instructions See Instruction List Nesting levels 8 System functions (SFCs) See Instruction List System function blocks (SFBs) See Instruction List User program security Password protection Voltages, Currents Power supply 24V DC  Permissible range 20.4 V to 28.8 V Current consumption (idle) typical 0.7 A Inrush current typical 8A l 2 t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A, Type B or C PD supply at MPI (15 to 30V DC) max. 200 mA Power losses typical 8 W Battery Yes  Backup margin at 25 C and continuous CPU buffering min. 1 year  Battery shelf life at 25C approx. 5 years Accumulator Yes  Clock back-up period – at 0 to 25C Approx. 4 weeks – at 40 C Approx. 3 weeks – at 60  C Approx. 1 week  Battery charging time Approx. 1 hour CPUs 1-43 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.4.4 CPU 314IFM Special Features  Integrated I/Os (wired with 40-pole front connector) Details on analog value processing and how to connect measuring transducers, load and actuators to analog I/O is found in the Module Data reference manual. Figures 1-14 and 1-15 on page 1-59 show wiring examples. Memory card The CPU 314 IFM is available in 2 versions: with and without Memory Card slot.  With slot for memory card: 6ES7 314-5AE10-0AB0  Without slot for memory card: 6ES7 314-5AE0x-0AB0 Integrated Functions of the CPU 314 IFM Integrated Functions Description Process interrupt Interrupt input means: inputs configured with this function trigger a process interrupt at the corresponding signal edge. If you wish to use the digital inputs 126.0 to 126.3 as interrupt inputs, you must program these using STEP 7. Note: Your user program should access analog inputs of your CPU individually per L PEW in order to avoid an increase of interrupt response times. Double-word addressing can increase the access times by up to 200
s! Counter The CPU 314 IFM offers these special functions as an alternative at the Frequency meter digital inputs 126.0 to 126.3. For a description of these special Counter A/B functions, please refer to the Integrated Functions Manual. Positioning CONT_C These functions are not restricted to specific inputs and outputs of the CONT_S CPU 314 IFM. For a description of these functions, please refer to the PULSEGEN System and Standard Functions Reference Manual. CPUs 1-46 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Front View of the CPU 314 IFM IN OUTOUT M L +M
    
Status and error LEDs  Mode selector switch  Compartment for backup battery or rechargeable battery  Jumper (removable)   Connection for power supply and system ground  Multipoint interface MPI  Integrated I/Os  Memory Card slot (only -5AE10-) Figure 1-10 Front View of the CPU 314 IFM CPUs 1-47 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the CPU 314 IFM CPU and Product Version MLFB 6ES7 314-...-0AB0  Hardware version -5AE03- 01 -5AE10- 01  Firmware version V 1.1.0 V 1.1.0  Matching programming package STEP 7 V5.0, Service Pack 3 Memory Work memory  integral 32 KB 32 KB  Expandable no No Load memory  integral 48 KB RAM 48 KB FEPROM 48 KB RAM  Expandable FEPROM no Up to 4 MB  Expandable RAM no No Backup Yes  With battery All data  Without battery 144 bytes Processing times Processing times for  Bit instructions 0.3
s minimum  Word instructions 1
s minimum  Double integer math 2
s minimum  Floating-point math instructions 50
s minimum Timers/Counters and their retentive characteristics S7 counters 64  Adjustable retentivity from C 0 to C 63  Preset from C 0 to C 7  Counting range 0 to 999 IEC Counters Yes  Type SFB S7 timers 128  Adjustable retentivity from T 0 to T 7  Preset No retentive times  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFB Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) max. 2 DB, 144 bytes Bit memories 2048  Adjustable retentivity MB 0 to MB 143  Preset MB 0 to MB 15 Clock memories 8 (1 memory byte) Data blocks max. 127 (DB 0 reserved)  Size max. 8 KB  Adjustable retentivity max. 2 DB, 144 data bytes  Preset No retentivity Local data (non-alterable) 1536 bytes  Per priority class 256 bytes Blocks OBs See Instruction List  Size max. 8 KB Nesting depth  Per priority class 8  additional levels within an error OB 4 FBs 128  Size max. 8 KB FCs 128  Size max. 8 KB Address areas (I/O) Peripheral address area  Digital 0 to 123/0 to 123 – integral 124 to 127/124, 125  Analog 256 to 751/256 to 751 – integral 128 to 135/128, 129 Process image (cannot be customized) 128 bytes/128 bytes Digital channels max. 992+20 integral/ max. 992+16 integral Analog channels max. 248+4 integral/ max. 124+1 integral CPUs 1-48 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Configuration Rack max. 4 Modules per module rack max. 8; max. 7 in module rack 3 Number of DP masters  integral None  via CP 1 S7 message functions Simultaneously active Alarm-S blocks max. 40 Time Real-time clock Yes  Backed-up Yes  Accuracy See Section 1.1.6 Operating hours counter 1  Number 0  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master  On MPI Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DBs, timers, counters  Number – Monitor Variables – Modify Variables max. 30 max. 14 Force Yes  Variable Inputs, outputs  Number max. 10 Monitor block Yes Single sequence Breakpoint Yes 2 Diagnostic buffer Yes  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 1  Size of GD packets max. 22 bytes – Number of which consistent 8 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 32 bytes for X/I_PUT/_GET; 76 bytes for X_SEND/_RCV S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent 32 bytes S7-compatible communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Standard communication Yes (via FC and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Number of connection resources 12 for PD/OP/S7 basic/S7 communication  Reservation for – PD communication User-definable Default max. 11 from 1 to 11 1 – OP communication User-definable Default max. 11 from 1 to 11 1 – S7 basic communication User-definable Default max. 8 from 0 to 8 8 Interfaces 1. Interface Functionality  MPI Yes  DP Master No  DP Slave No  Galvanically isolated No CPUs 1-51 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Analog Inputs of the CPU 314IFM Module-Specific Data Number of inputs 4 Cable length  Shielded max. 100 m (109yd.) Voltages, Currents, Potentials Galvanic isolation  between channels and backplane bus Yes Permissible potential difference  between inputs and MANA (UCM)  between MANA and Minternal (UISO) 1.0V DC 75V DC 60V AC Insulation tested at 500V DC Analog Value Generation Measurement principle Conversion time/Resolution (per channel)  Basic conversion time  Resolution (inc. overdrive range) Momentary value encoding (successive approximation) 100
s 11 bits + sign bit Interference Suppression, Error Limits Interference voltage suppression  Common-mode interference (UCM<1.0 V) > 40 dB Crosstalk between the inputs > 60 dB Operational error limits (throughout temperature range, relative to input range)  Voltage input  Current input
1.0 %
1.0 % Interference Suppression, Error Limits, Conti- nued Basic error limits (operational limit at 25°C, relative to input range)  Voltage input  Current input
0.9 %
0.8 % Temperature error (referred to input range)

0.01 %/K Linearity error (referred to input range)
0.06 % Accuracy of reproducibility (in transient state at 25°C, referring to input range)
0.06 % Status, Interrupts, Diagnostics Interrupts None Diagnostic functions None Sensor Selection Data Input ranges (rated value)/input resistance  Voltage  Current

10 V/50 k

20 mA/105.5  Permissible input voltage for voltage input (destruction limit) max. 30 V continuous; 38 V for max. 1 s (pulse duty factor 1:20) Permissible input current for current input (destruction limit) 34 mA Connecting signal generators  for voltage measurement  for current measurement as 2-pole measurement transducer as 4-pole measurement transducer Possible Not possible Possible CPUs 1-52 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Analog Output of the CPU 314IFM Module-Specific Data Number of outputs 1 Cable length  Shielded max. 100 m (109yd.) Voltages, Currents, Potentials Galvanic isolation  Between channels and backplane bus Yes Permissible potential difference  between MANA and Minternal (UISO) 75V DC 60V AC Insulation tested at 500V DC Analog Value Generation Resolution (inc. overdrive range) Conversion time Settling time  For resistive load  For capacitive load  For inductive load Connection of substitute values 11 bits + sign bit 40
s 0.6 ms 1.0 ms 0.5 ms No Interference Suppression, Error Limits Operational error limits (throughout temperature range, relative to output range)  Voltage output  Current output
1.0 %
1.0 % Basic error limit (operational limit at 25°C, relative to output range)  Voltage output  Current output
0.8 %
0.9 % Temperature error (relative to output range)

0.01 %/K Linearity error (relative to output range)
0.06 % Accuracy of reproducibility (in transient state at 25°C, relative to output range)
0.05 % Output ripple; Range of 0 to 50 kHz (referring to output range)
0.05 % Status, Interrupts; Diagnostics Interrupts None Diagnostic functions None Actuator Selection Data Output ranges (rated values)  Voltage  Current

10 V

20 mA Load impedance  For voltage output capacitive load  For current output inductive load min. 2.0 k max. 0.1
F max. 300  max. 0.1 mH Voltage output  Short-circuit protection  Short-circuit current Yes max. 40 mA Current output  Idle voltage max. 16 V Destruction limit for externally applied voltages/currents  Voltages at the output with ref. to MANA  Current max.

15 V, continuous;

15 V for max. 1 s (duty factor 1:20) max. 30 mA Connecting actuators  for voltage output 2-wire connection 4-wire connection  for current output 2-wire connection Possible Not possible Possible CPUs 1-53 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Technical Specifications of the Special Inputs of the CPU 314IFM Module-Specific Data Number of inputs 4 I 126.0 to 126.3 Cable length  Shielded max. 100 m (109yd.) Voltages, Currents, Potentials Number of inputs that can be triggered simultaneously  (horizontal configuration) up to 60°C  (vertical configuration) up to 40°C 4 4 4 Status, Interrupts; Diagnostics Status display 1 green LED per channel Interrupts  Process interrupt Configurable Diagnostic functions None Sensor Selection Data Input voltage  Rated value  For “1” signal  For “0” signal 24V DC 11 V to 30 V 18 to 30 V with angular encoder and integrated ”Positioning” function -3 to 5 V Input current  For “1” signal typical 6.5 mA Input delay time  For “0” to “1”  For “1” to “0” < 50
s (typical 17
s) < 50
s (typical 20
s) Input characteristic to IEC 1131, Type 2 Connection of 2-wire BEROs  Permissible quiescent current Possible max. 2 mA Time, Frequency Internal conditioning time for  Interrupt processing max. 1.2 ms Input frequency  10 kHz CPUs 1-56 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Wiring diagram of the CPU 314 IFM Figure 1-11 shows the wiring diagram of the CPU 314 IFM. For the connection of integrated I/O you require two 40-pole front connectors (Order no.: 6ES7392-1AM00-0AA0). Always wire up digital inputs 126.0 to 126.3 with shielded cable due to their low input delay time. ! Caution Wiring errors at the analog outputs can cause the integrated analog I/O of the CPU to be destroyed! (for example, if the interrupt inputs are wired by mistake to the analog output). The analog output of the CPU is only indestructible up to 15 V (output with respect to MANA). 1M 1 L+ 3L+ 3M 2L+ 2M 1 L+ MANA Special inputs Analog outputs Analog inputs I 126.0 I 126.1 I 126.2 I 126.3 PQW 128 PIW 128 PIW 130 PIW 132 PIW 134 AOU AOI AIU AII AI- AIU AII AI- AIU AII AI- AIU AII AI- 124.0 124.1 124.2 124.3 124.4 124.5 124.6 124.7 125.0 125.1 125.2 125.3 125.4 125.5 125.6 125.7 124.0 124.1 124.2 124.3 124.4 124.5 124.6 124.7 125.0 125.1 125.2 125.3 125.4 125.5 125.6 125.7 Digital inputs Digital outputs Figure 1-11 Wiring diagram of the CPU 314 IFM CPUs 1-57 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Basic Circuit Diagrams of the CPU 314 IFM Figures 1-12 and 1-13 show the basic circuit diagrams for the integrated inputs/outputs of the CPU 314 IFM. L + DAC Internal supply +  Ref M ADC V A MANA MANA Multiplexer V A MANA C P U in te rf ac e C P U in te rf ac e M M Figure 1-12 Basic Circuit Diagram of the CPU 314 IFM (Special Inputs and Analog Inputs/Outputs) CPUs 1-58 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1 L+ CPU interface 24V 1M M 2L+ M 2M 3M 24V 24V 3L+ M Figure 1-13 Basic Circuit Diagram of the CPU 314 IFM (Digital Inputs/Outputs) CPUs 1-61 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Configuration Rack max. 4 Modules per module rack max. 8 Number of DP masters  integral None  via CP 1 S7 message functions Simultaneously active Alarm-S blocks 50 Time Real-time clock Yes  Backed-up Yes  Accuracy See Section 1.1.6 Operating hours counter 1  Number 0  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master  On MPI Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DPs, timers, counters  Number – Monitor Variables – Modify Variables max. 30 max. 14 Force Yes  Variable Inputs, outputs  Number max. 10 Monitor block Yes Single sequence Breakpoint Yes 2 Diagnostic buffer Yes  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 1  Size of GD packets max. 22 bytes – Number of which consistent 8 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 32 bytes for X/I_PUT/_GET; 76 bytes for X_SEND/_RCV S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent 32 bytes S7-compatible communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Standard communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Number of connection resources 12 for PD/OP/S7 basic/S7 communication  Reservation for – PD communication User-definable Default max. 11 from 1 to 11 1 – OP communication User-definable Default max. 11 from 1 to 11 1 – S7 basic communication User-definable Default max. 8 from 0 to 8 8 Interfaces 1. Interface Functionality  MPI Yes  DP Master No  DP Slave No  Galvanically isolated No CPUs 1-62 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 MPI  Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server)  Transmission rates 19.2; 187.5 Kbps Dimensions Assembly dimension BHT (mm) 80125130 Weight Approx. 0.53 kg Programming Programming language STEP 7 Stored instructions See Instruction List Nesting levels 8 System functions (SFCs) See Instruction List System function blocks (SFBs) See Instruction List User program security Password protection Voltages, Currents Power supply 24V DC  Permissible range 20.4 to 28.8 V Current consumption (idle) typical 7.0 A Inrush current typical 8A l 2 t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A Type B or C PD supply at MPI (15 to 30V DC) max. 200 mA Power losses typical 8 W Battery Yes  Backup margin at 25 C and continuous CPU buffering min. 1 year  Battery shelf life at 25C approx. 5 years Accumulator Yes – at 0 to 25C Approx. 4 weeks – at 40 C Approx. 3 weeks – at 60  C Approx. 1 week  Battery charging time Approx. 1 hour CPUs 1-63 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.4.6 CPU 315-2 DP DP master or DP slave You can operate the CPU 315-2 DP on your 2nd interface (PROFIBUS-DP interface) as DP Master or DP Slave in a PROFIBUS-DP network. For details on PROFIBUS-DP characteristics of CPU 315-2 DP refer to Chapter 2. CPU 315-2 DP, Technical Data CPU and Product Version MLFB  Hardware version 6ES7 315-2AF03-0AB0 01  Firmware version V 1.1.0  Matching programming package STEP 7 V 5.0; Service Pack 03 Memory Work memory  integral 64 KB  Expandable no Load memory  integral 96 KB RAM  Expandable FEPROM Up to 4 MB  Expandable RAM no Backup Yes  With battery All data  Without battery 4736 bytes Processing times Processing times for  Bit instructions 0.3
s minimum  Word instructions 1
s minimum  Double integer math 2
s minimum  Floating-point math instructions 50
s minimum Timers/Counters and their retentive characteristics S7 counters 64  Adjustable retentivity from C 0 to C 63  Preset from C 0 to C 7  Counting range 0 to 999 IEC Counters Yes  Type SFB S7 timers 128  Adjustable retentivity from T 0 to T 127  Preset No retentive times  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFB Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) 4736 bytes Bit memories 2048  Adjustable retentivity MB 0 to MB 255  Preset MB 0 to MB 15 Clock memories 8 (1 memory byte) Data blocks max. 255 (DB 0 reserved)  Size max. 16 KB  Adjustable retentivity 8 DB; max. 4096 data bytes  Preset No retentivity Local data (non-alterable) max. 1536 bytes  Per priority class 256 bytes Blocks OBs See Instruction List  Size max. 16 KB Nesting depth  Per priority class 8  additional levels within an error OB 4 FBs max. 192  Size max. 16 KB FCs max. 192  Size max. 16 KB CPUs 1-66 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 1.4.7 CPU 316-2 DP DP master or DP slave You can operate the CPU 316-2 DP on your 2nd interface (PROFIBUS-DP interface) as DP Master or DP Slave in a PROFIBUS-DP network. For details on PROFIBUS-DP characteristics of CPU 316-2 DP refer to Chapter 2. CPU 316-2 DP, Technical Data CPU and Product Version MLFB  Hardware version 6ES57 316-2AG00-0AB0 01  Firmware version V 1.1.0  Matching programming package STEP 7 V 5.0; Service Pack 03 Memory Work memory  integral 128 KB  Expandable no Load memory  integral 192 KB  Expandable FEPROM Up to 4 MB  Expandable RAM no Backup Yes  With battery All data  Without battery 4736 bytes Processing times Processing times for  Bit instructions 0.3
s minimum  Word instructions 1
s minimum  Double integer math 2
s minimum  Floating-point math instructions 50
s minimum Timers/Counters and their retentive characteristics S7 counters 64  Adjustable retentivity from C 0 to C 63  Preset from C 0 to C 7  Counting range 0 to 999 IEC Counters Yes  Type SFB S7 timers 128  Adjustable retentivity from T 0 to T 127  Preset No retentive times  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFB Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) 4736 bytes Bit memories 2048  Adjustable retentivity MB 0 to MB 255  Preset MB 0 to MB 17 Clock memories 8 (1 memory byte) Data blocks 511 (DB 0 reserved)  Size max. 16 KB  Adjustable retentivity max. 8 DB 4096 data bytes  Preset No retentivity Local data (non-alterable) max. 1536 bytes  Per priority class 256 bytes Blocks OBs See Instruction List  Size max. 16 KB Nesting depth  Per priority class 8  additional levels within an error OB 4 FBs max. 256  Size max. 16 KB FCs max. 256  Size max. 16 KB CPUs 1-67 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Address areas (I/O) Peripheral address area, digital/analog 2 KB/2 KB (freely addressable)  Distributed 2 KB/2 KB Process image (cannot be customized) 128/128 bytes Digital channels max. 16384 (minus 1 byte diagnostic address per DP slave)/16384  Centralized max. 1024/1024 Analog channels max. 1024 (minus 1 byte diagnostic address per DP slave)/1024  Centralized max. 256/128 Configuration Rack max. 4 Modules per Rack max. 8 Number of DP masters  integral 1  via CP 1 S7 message functions Simultaneously active Alarm-S blocks max. 50 Time Real-time clock Yes  Backed-up Yes  Accuracy See Section 1.1.6 Operating hours counter 1  Number 0  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master  On MPI Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DBs, timers, counters  Number – Monitor Variables – Modify Variables max. 30 max. 14 Force Yes  Variable Inputs, outputs  Number max. 10 Monitor block Yes Single sequence Breakpoint Yes 2 Diagnostic buffer Yes  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 1  Size of GD packets max. 22 bytes – Number of which consistent 8 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 32 bytes for X/I_PUT/_GET; 76 bytes for X_SEND/_RCV S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent 32 bytes S7-compatible communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Standard communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Number of connection resources 12 for PD/OP/S7 basic/S7 communication  Reservation for – PD communication User-definable Default max. 11 from 1 to 11 1 – OP communication User-definable Default max. 11 from 1 to 11 1 – S7 basic communication User-definable Default max. 8 from 0 to 8 8 Routing connections max. 4 CPUs 1-68 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Interfaces 1. Interface Functionality  MPI Yes  DP Master No  DP Slave No  Galvanically isolated No MPI No  Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server)  Transmission rates 19.2; 187.5 Kbps 2. Interface Functionality  DP Master Yes  DP Slave Yes – Status/Modify; Program; Routing Yes, can be activated  Direct data exchange Yes  Point-to-point connection No  Default setting None  Galvanically isolated Yes DP Master  Services – Equidistance Yes – SYNC/FREEZE Yes – Activation/deactivat ion of DP slaves Yes  Transmission rates Up to 12 Mbps  Number of DP slaves max. 125  Address area max. 2 KB I/2 KB O  User data per DP slave max. 244 bytes I and 244 bytes O DP Slave  Services – Status/Modify; Program; Routing Yes, can be activated  Device master file Siem806f.gsg  Transmission rate Up to 12 Mbps  Transfer memory 244 bytes I/244 bytes O – Address areas max. 32 with max. 32 bytes each Dimensions Assembly dimension BHT (mm) 80125130 Weight Approx. 0.53 kg Programming Programming language STEP 7 Stored instructions See Instruction List Nesting levels 8 System functions (SFCs) See Instruction List System function blocks (SFBs) See Instruction List User program security Password protection Voltages, Currents Power supply 24V DC  Permissible range 20.4 to 28.8 V Current consumption (idle) typical 0.9A Inrush current typical 8A l 2 t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A, Type B or C PD supply at MPI (15 to 30V DC) max. 200 mA Power losses typical 10 W Battery Yes  Backup margin at 25 C and continuous CPU buffering min. 1 year  Battery shelf life at 25C approx. 5 years Accumulator Yes  Clock back-up period – at 0 to 25C Approx. 4 weeks – at 40 C Approx. 3 weeks – at 60  C Approx. 1 week  Battery charging time Approx. 1 hour CPUs 1-71 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 CPU 318-2, Technical Data CPU and Product Version MLFB  Hardware version 6ES7 318-2AJ00-0AB0 03  Firmware version V 3.0  Matching programming package STEP 7 V 5.1 + Service Pack 02 Memory Work memory  integral 256 KB data/ 256 KB code  Expandable no Load memory  integral 64 KB  Expandable FEPROM Up to 4 MB  Expandable RAM Up to 2 MB Backup Yes  With battery All data  Without battery max. 11 KB Processing times Processing times for  Bit instructions 0.1
s minimum  Word instructions 0.1
s minimum  Double integer arithmetic 0.1
s minimum  Floating-point arithmetic 0.6
s minimum Timers/Counters and their retentive characteristics S7 counters 512  Adjustable retentivity from C 0 to C 511  Preset from C 0 to C 7  Counting range 0 to 999 IEC Counters Yes  Type SFB S7 timers 512  Adjustable retentivity from T 0 to T 511  Preset No retentive times  Timing range 10 ms to 9990 s IEC Timers Yes  Type SFB Data areas and their retentive characteristics Retentive data area as a whole (inc. flags, timers, counters) max. 11 KB Bit memories 8192  Adjustable retentivity MB 0 to MB 1023  Preset MB 0 to MB 15 Clock memories 8 (1 memory byte) Data blocks 2047 (DB 0 reserved)KB  Size max. 64 KB  Adjustable retentivity max. 8 DB, max. 8192 data bytes  Preset No retentivity Local data (alterable) max. 8192 bytes  Preset 3584 bytes  Per priority class 256 bytes (expandable to 8192 bytes) Blocks OBs See Instruction List  Size max. 64 KB Nesting depth  Per priority class 16  additional levels within an error OB 3 FBs max. 1024  Size max. 64 KB FCs max. 1024  Size max. 64 KB Address areas (I/O) Peripheral address area, digital/analog max. 8 KB/8 KB (freely addressable)  Distributed – MPI/DP Interface max. 2 KB/2 KB – DP interface max. 8 KB/8 KB Process image (configurable) 2048/2048 bytes  Preset 256/256 bytes Digital channels max. 65536 (minus 1 byte diagnostic address per DP slave)/65536  Centralized max. 1024/1024 Analog channels max. 4096/4096  Centralized max. 256/128 CPUs 1-72 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Configuration Rack max. 4 Modules per module rack max. 8 Number of DP masters  integral 2  via CP 2 S7 message functions Simultaneously active Interrupt S function blocks and Interrupt D function blocks max. 100 Time Real-time clock Yes  Backed-up Yes  Accuracy See Section 1.1.6 Operating hours counter 8  Number 0 to 7  Value range 0 to 32767 hours  Selectivity 1 hour  Retentive Yes Clock synchronisation Yes  On PLC Master/Slave  via MPI  via DP Master/Slave Master/Slave Testing and commissioning functions Status/Modify Variables Yes  Variable Inputs, outputs, flags, DBs, timers, counters  Number max. 70 Force Yes  Variable Inputs, outputs, flags, peripheral inputs, peripheral outputs  Number max. 256 Monitor block Yes Single sequence Breakpoint Yes 4 Diagnostic buffer  Number of entries (non-alterable) 100 Communication functions PD/OP communication Yes Global data communication Yes  Number of GD packets – Sender 1 – Receiver 2  Size of GD packets 54 bytes – Number of which consistent 32 bytes S7 basic communication Yes  User data per job max. 76 bytes – Number of which consistent 76 bytes S7 communication Yes (server)  User data per job max. 160 bytes – Number of which consistent Byte, Word, Double word S7-compatible communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Standard communication Yes (via CP and loadable FC)  User data per job Dependent on CP – Number of which consistent Dependent on CP Interfaces 1. Interface Functionality  MPI Yes  DP Master Yes  DP Slave Yes  Direct data exchange Yes  Default setting MPI  Electrically isolated Yes Number of connections max. 32; – Of these, the following are reserved: 1 PD connection 1 OP connection MPI  Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server)  Transmission rates Up to 12 Mbps CPUs 1-73 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 DP Master  Services – Equidistance Yes – SYNC/FREEZE Yes – Activation/deactivat ion of DP slaves Yes  Transmission rates Up to 12 Mbps  Address area max. 2 KB I/2 KB O  User data per DP slave max. 244 bytes I and 244 bytes O DP Slave  Services – Status/Modify; Program; Routing Yes, can be activated  Device master file siem807f.gsg  Transmission rate Up to 12 Mbps  Transfer memory 244 bytes I/244 bytes O 2. Interface Functionality  DP Master Yes  DP Slave Yes – Status/Modify; Program; Routing Yes, can be activated  Direct data exchange Yes  PtP Connection No  Default setting None  Galvanically isolated Yes Number of connections max. 16 – Of these, the following are reserved: 1 PD connection 1 OP connection DP Master  Services – PD/OP communication Yes – Equidistance Yes – SYNC/FREEZE Yes – Activation/deactivat ion of DP slaves Yes  Transmission rates Up to 12 Mbps  Number of DP slaves max. 125  Address area max. 8 KB I/8 KB O  User data per DP slave max. 244 bytes I and 244 bytes O DP Slave  Services – Status/Modify; Program; Routing  GSD file  Transmission speed  Transfer memory Yes, can be activated siem807f.gsg Up to 12 Mbps 244 bytes I/244 bytes O Dimensions Assembly dimension BHT (mm) 160125130 Weight Approx. 0.93 kg Programming Programming language STEP 7 Stored instructions See Instruction List Nesting levels 16 System functions (SFCs) See Instruction List System function blocks (SFBs) See Instruction List User program security Password protection Voltages, Currents Power supply 24V DC  Permissible range 20.4 V to 28.8 V Current consumption (idle) typical 1.2 A Inrush current typical 8A l 2 t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A, Type B or C PD supply at MPI (15 to 30V DC) max. 200 mA Power losses typical 12 W Battery Yes  Backup margin at 25 C and continuous CPU buffering min. 1 year  Battery shelf life at 25C approx. 5 years Accumulator Yes  Clock back-up period – at 0 to 25C Approx. 4 weeks – at 40 C Approx. 3 weeks – at 60  C Approx. 1 week  Battery charging time Approx. 1 hour CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-2 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 2.1 Information on DPV1 Functionality The aim The EN50170 Standard for Distributed Peripherals was subject to further development. All changes were incorporated in IEC 61158 / EN 50170, Volume 2, PROFIBUS. In order to simplify matters we now refer to DPV1 Mode. How do I identify a DPV1 Master/Slave? DP Master CPUs of the S7-400 family and the CPU 318-2, respectively with integrated DP interface, support DPV1 Master functionality as of Firmware Version 3.0.0. DP Slaves, listed in the STEP 7 hardware catalog under their family name can be identified as DPV1 Slaves with the help of the info text. DP Slaves implemented in STEP 7 via GSD files support V1 functionality as of GSD Revision 3. As of which STEP 7 version is migration to DPV1 mode possible? As of STEP 7 V5.1, Servicepack 2. Which operating modes are available for DPV1 modules? You are using a DPV1 automation module, but do not want to migrate to DPV1 mode. In this case you use S7 compatible mode. In this mode, the automation module is compatible to EN50170. In this case, however, you cannot utilize full DPV1 functionality. You could, for example, use the new SFBs 52...54. However, default values are written to non-existing data. You are using a DPV1 compatible automation module and want to migrate to DPV1 mode. In this case, use DPV1 mode for full functionality. In your station you can continue using automation modules not supporting DPV1 as usual. Can I use all previous slaves after migration to DPV1 mode? Yes, without restriction. The only difference here is that your previous slaves do not support extended DPV1 functions. CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-3 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Can I use DPV1 Slaves without this migration? Yes, without restriction. In this case, DPV1 Slaves behave as conventional Slaves. SIEMENS DPV1 Slaves can also be operated in S7 compatible mode. For DPV1 Slaves of other manufacturers you require a GSD file to EN50170 below Revision 3. DPV1 – station-wide. You must convert the complete station to DPV1 mode if you migrate to DPV1. In STEP 7 you can configure this mode in the HW Config module (DP Mode). Details on migration to DPV1 mode are found in our Customer Support under FAQ topic ID: 7027576 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-4 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 2.2 DP Address Areas of the CPUs 31x-2 Address areas of CPUs 31x-2 Address area 315-2 DP 316-2DP 318-2 DP address area for I/Os 1024 bytes 2048 bytes 8192 bytes of these in the I/O process images Bytes 0 to 127 Bytes 0 to 127 Bytes 0 to 255 (default) Can be set up to byte 2047 In the input address area, DP diagnostic addresses occupy 1 byte for the DP master and for each DP slave. Under these addresses, for example, you can call DP standard diagnostics for the respective nodes (LADDR parameter of SFC13). The DP diagnostic addresses are specified during configuration. If you do not specify any DP diagnostic addresses, STEP 7 assigns these addresses, in decrements starting at the highest byte. Configuring modules with addresses assigned to the peripheral area Always configure a module address in a peripheral area either completely inside or completely outside of the process image. Otherwise, consistency is not ensured and corrupted data might be generated. CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-7 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Reading Diagnostic Data with STEP 7 Table 2-2 Reading Diagnostic Data with STEP 7 DP Master Modules or registers in STEP 7 Application See... CPU 31x-2 ”DP slave diagnostics” tab Display slave diagnostic data as plain text on the STEP 7 user interface See “Diagnosis of Hardware” in the STEP 7 Online Help and STEP 7 User Manual SFC 13 “DPNRM_DG” Reading out slave diagnosis (store in the data area of the user program) Configuration for the CPU 31x-2, see Section 2.6.4; SFC, see System and Standard Functions Reference Manual Configuration for other slaves, see their description SFC 59 “RD_REC” Read out data records of the S7 diagnosis (store in the data area of the user program) SFC 51 “RDSYSST” Read out system state sub-lists. In the diagnostics interrupt with the SSL ID W#16#00B4, call SFC51 and read out the SSL (system diagnostic list) of the slave CPU. SFB 52 “RDREC” (only 318-2) Applicable to DPV1 environment: Read out data records of the S7 diagnosis (store in the data area of the user program) System and Standard Functions Reference Manual SFB 54 “RALRM” (only 318-2) Applicable to DPV1 environment: Read out interrupt information within the corresponding interrupt OB Evaluating Diagnostics in the User Program The following figures show you how to evaluate the diagnosis in the user program. Note the order number for the CPU 315-2DP: CPU 315-2DP < 6ES7 315-2AF03-0AB0 CPU 315-2DP as of 6ES7315-2AF03-0AB0 CPU 316-2DP as of 6ES7316-2AG00-0AB0 CPU 316-2 as of 6ES7318-2AJ00-0AB0 ...see Figure 2-1 on page 2-8 ...see Figure 2-2 on page 2-9 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-8 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Read out OB82_MDL_ADDR (Diagnostic address of the DP slave = STEP 7 diagnostic address) Diagnostic event OB82 is called Read out the parameter OB 82_MDL_TYPE in the local data of OB 82: The module class is in the bits 0 to 3 (DP slave type) 0011 = DP slave according to the standard 1011 = CPU as DP slave (I slave) Call SFC 13  Enter the diagnostic address in the LADDR parameter Read out OB82_MDL_ADDR (Diagnostic address of the DP slave = STEP 7 diagnostic address) Call SFC 51  Enter the diagnostic address in the INDEX parameter (always the input address here) Enter the ID W#16#00B3 in the SZL_ID parameter (=diagnostic data of a module) Call SFC 13  Enter the diagnostic address in the LADDR parameter CPU 315-2DP smaller than 6ES7 315-2AF03-0AB0 Read out OB82_MDL_ADDR and Read out OB82_IO_FLAG (= identifier I/O module) Enter bit 0 of OB82_IO_Flag as bit 15 in OB82_MDL_ADDR Result: Diagnostics address ”OB82_MDL_ADDR*” For the diagnosis of the modules involved: Call SFC 51  Enter the diagnostic address “OB82_MDL_ADDR*” in the INDEX parameter Enter the ID W#16#00B3 in the SZL_ID parameter (=diagnostic data of a module) Other ID: S7-DP Slave Figure 2-1 Diagnostics with CPU 315-2DP < 315-2AF03 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2-9 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Diagnostic event Read out OB82_MDL_ADDR and Read out OB82_IO_FLAG (= identifier I/O module) For diagnosis of the whole DP slave: Call SFC 13  Enter the diagnostic address “OB82_MDL_ADDR*” in the LADDR parameter Enter bit 0 of OB82_IO_Flag as bit 15 in OB82_MDL_ADDR Result: Diagnostics address ”OB82_MDL_ADDR*” For the diagnosis of the modules involved: Call SFC 51  Enter the diagnostic address “OB82_MDL_ADDR*” in the INDEX parameter Enter the ID W#16#00B3 in the SZL_ID parameter (=diagnostic data of a module) CPU 315-2DP as of 6ES7 315-2AF03-0AB0 CPU 3162DP; 318-2 OB82 is called For the diagnostics of the respective modules: call SFB 54 (in DPV1 mode)  Set MODE = 1 Diagnostic data is written to the parameters TINFO and AINFO. only 318-2 Figure 2-2 Diagnostics with CPU 31x-2 (315-2DP as of 315-2AF03)