pratica01 Microcontrolador PIC18f2550 - hlppic18conf

pratica01 Microcontrolador PIC18f2550 - hlppic18conf

PIC18F2550 PLL Prescaler Selection bits:

CPU System Clock Postscaler:

USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): Oscillator Selection bits:

Fail-Safe Clock Monitor Enable bit: Internal/External Oscillator Switchover bit:

PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) PLLDIV = 2 Divide by 2 (8 MHz oscillator input) PLLDIV = 3 Divide by 3 (12 MHz oscillator input) PLLDIV = 4 Divide by 4 (16 MHz oscillator input) PLLDIV = 5 Divide by 5 (20 MHz oscillator input) PLLDIV = 6 Divide by 6 (24 MHz oscillator input) PLLDIV = 10 Divide by 10 (40 MHz oscillator input) PLLDIV = 12 Divide by 12 (48 MHz oscillator input)

USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2

FOSC = XT_XT XT oscillator, XT used by USB FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB FOSC = ECIO_EC External clock, port function on RA6, EC used by USB FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB FOSC = INTOSC_XT Internal oscillator, XT used by USB FOSC = INTOSC_HS Internal oscillator, HS used by USB FOSC = HS HS oscillator, HS used by USB FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB

FCMEN = OFF Fail-Safe Clock Monitor disabled FCMEN = ON Fail-Safe Clock Monitor enabled

Power-up Timer Enable bit: Brown-out Reset Enable bits:

Brown-out Voltage bits:

USB Voltage Regulator Enable bit:

Watchdog Timer Enable bit: Watchdog Timer Postscale Select bits:

IESO = OFF Oscillator Switchover mode disabled IESO = ON Oscillator Switchover mode enabled

PWRT = ON PWRT enabled PWRT = OFF PWRT disabled

BOR = OFF Brown-out Reset disabled in hardware and software BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)

BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SBOREN is disabled)

BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)

BORV = 0 Maximum setting BORV = 1

BORV = 2 BORV = 3 Minimum setting

VREGEN = OFF USB voltage regulator disabled VREGEN = ON USB voltage regulator enabled

WDT = OFF HW Disabled - SW Controlled WDT = ON HW Enabled - SW Disabled

MCLR Pin Enable bit:

Low-Power Timer 1 Oscillator Enable bit:

PORTB A/D Enable bit:

CCP2 MUX bit:

Stack Full/Underflow Reset Enable bit:

Single-Supply ICSP Enable bit:

Extended Instruction Set Enable bit:

Background Debugger Enable bit:

Code Protection bit Block 0: Code Protection bit Block 1:

MCLRE = OFF RE3 input pin enabled; MCLR disabled MCLRE = ON MCLR pin enabled; RE3 input pin disabled

LPT1OSC = OFF Timer1 configured for higher power operation LPT1OSC = ON Timer1 configured for low-power operation

PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset

CCP2MX = OFF CCP2 input/output is multiplexed with RB3 CCP2MX = ON CCP2 input/output is multiplexed with RC1

STVREN = OFF Stack full/underflow will not cause Reset STVREN = ON Stack full/underflow will cause Reset

LVP = OFF Single-Supply ICSP disabled LVP = ON Single-Supply ICSP enabled

XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) XINST = ON Instruction set extension and Indexed Addressing mode enabled

DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

Code Protection bit Block 2:

Code Protection bit Block 3:

Boot Block Code Protection bit:

Data EEPROM Code Protection bit:

Write Protection bit Block 0:

Write Protection bit Block 1:

Write Protection bit Block 2:

Write Protection bit Block 3:

Boot Block Write Protection bit:

Configuration Register Write Protection bit: Data EEPROM Write Protection bit:

CPB = ON Boot block (0-0007FFh) code-protected CPB = OFF Boot block (0-0007FFh) not code-protected

CPD = ON Data EEPROM code-protected CPD = OFF Data EEPROM not code-protected

WRT0 = ON Block 0 (000800-001FFFh) write-protected WRT0 = OFF Block 0 (000800-001FFFh) not write-protected

WRT1 = ON Block 1 (002000-003FFFh) write-protected WRT1 = OFF Block 1 (002000-003FFFh) not write-protected

WRT2 = ON Block 2 (004000-005FFFh) write-protected WRT2 = OFF Block 2 (004000-005FFFh) not write-protected

WRT3 = ON Block 3 (006000-007FFFh) write-protected WRT3 = OFF Block 3 (006000-007FFFh) not write-protected

WRTB = ON Boot block (0-0007FFh) write-protected WRTB = OFF Boot block (0-0007FFh) not write-protected

WRTC = ON Configuration registers (300000-3000FFh) write-protected WRTC = OFF Configuration registers (300000-3000FFh) not write-protected

WRTD = ON Data EEPROM write-protected WRTD = OFF Data EEPROM not write-protected

Table Read Protection bit Block 0:

Table Read Protection bit Block 1:

Table Read Protection bit Block 2:

Table Read Protection bit Block 3: Boot Block Table Read Protection:

EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks

EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks

EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks

EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks

EBTRB = ON Boot block (0-0007FFh) protected from table reads executed in other blocks EBTRB = OFF Boot block (0-0007FFh) not protected from table reads executed in other blocks

Microchip Technology Inc.

Microchip Web Site

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