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P25-36149-0 MNL-01024-1.0

Copyright © 2007 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. ModelSim is a registered trademark of Mentor Graphics Corporation. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.

Version 7.2

Introduction to the Quartus® I Software

Introduction to the Quartus

® I Software Version x.x

Introduction to the

Quartus® I Software

Introduction to the Quartus I Software

Altera, the Altera logo, HardCopy, MAX, MAX+PLUS, MAX+PLUS I, MegaCore, MegaWizard, Nios, OpenCore, Quartus, QuartusII, the QuartusII logo, and SignalTap are registered trademarks of Altera Corporation in the United States and other countries. Avalon, ByteBlaster, ByteBlasterMV, Cyclone, Excalibur, IP MegaStore, Jam, LogicLock, MasterBlaster, SignalProbe, Stratix, and USB-Blaster are trademarks and/or service marks of Altera Corporation in the United States and other countries. Product design elements and mnemonics used by Altera Corporation are protected by copyright and/or trademark laws.

Altera Corporation acknowledges the trademarks and/or service marks of other organizations for their respective products or services mentioned in this document, specifically: ARM is a registered trademark and AMBA is a trademark of ARM, Limited. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation.

Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty. Testing and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer’s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used.

Altera products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Altera Corporation. As used herein:

1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights.

Documentation Conventionsxi
Chapter 1: Design Flow1
Graphical User Interface Design Flow3
EDA Tool Design Flow9
Design Methodologies and Planning14
Top-Down and Bottom-Up Design Methodologies15
Top-Down Incremental Compilation Flow15
Bottom-Up Incremental Compilation Flow17
Chapter 2: Command Line And Tcl Design Flows19
Command-Line Executables21
Using Standard Command-Line Commands & Scripts25
Using Tcl Commands27
Creating Makefile Scripts30
Chapter 3: Design Entry3
Creating a Project35
Using Revisions37
Using Version-Compatible Databases41
Converting MAX+PLUS I Projects42
Creating a Design43
Using the Quartus I Block Editor4
Using the Quartus I Text Editor45
Using the Quartus I Symbol Editor45
Using Verilog HDL, VHDL and AHDL46
Using the State Machine Editor47
Using Altera Megafunctions47
Using Intellectual Property (IP) Megafunctions48
Using the MegaWizard Plug-In Manager50
Instantiating Megafunctions in the QuartusII Software51
Instantiation in Verilog HDL & VHDL51
Using the Port & Parameter Definition51
Inferring Megafunctions52
Instantiating Megafunctions in EDA Tools52
Using the Black Box Methodology52
Instantiation by Inference53
Using the Clear Box Methodology53
Chapter 4: Constraint Entry57
Using the Assignment Editor59
Using the Pin Planner60


The Settings Dialog Box62
Assigning Design Partitions63
Assigning Design Partitions in the Project Navigator63
Assigning Design Partitions with the Design Partitions Window64
Importing Assignments65
Verifying Pin Assignments67
Chapter 5: Synthesis69
Using QuartusII VerilogHDL& VHDL Integrated Synthesis71
Using Other EDA Synthesis Tools74
Controlling Analysis & Synthesis7
Using Compiler Directives and Attributes7
Using Quartus I Logic Options78
Using QuartusII Synthesis Netlist Optimization Options80
Using the Design Assistant to Check DesignReliability81
Analyzing Synthesis Results With the Netlist Viewers83
The RTL Viewer83
The State Machine Viewer84
The Technology Map Viewer86
Chapter 6: Place and Route89
Performing a Full Incremental Compilation92
Analyzing Fitting Results93
Using the Messages Window to View Fitting Results93
Using the Report Window or Report File to View Fitting Results95
Using the Chip Planner to Analyze Results96
Using the Design Assistant to Check Design Reliability97
Optimizing the Fit97
Using Location Assignments98
Setting Options that Control Place & Route98
Setting Fitter Options98
Setting Physical Synthesis Optimization Options9
Setting Individual Logic Options that Affect Fitting9
Using the Resource Optimization Advisor100
Using the Design Space Explorer102
Preserving Assignments through Back-Annotation107
Chapter 7: Block-Based Design1
Quartus I Block-Based Design Flow112
Using LogicLock Regions113
Using LogicLock Regions in Top-Down Incremental Compilation Flows117
Exporting & Importing Partitions for Bottom-Up Design Flows118

IV■INTRODUCTION TO THE QUARTUS I SOFTWAREALTERA CORPORATION Preparing the Top-Level Design for a Bottom-Up Incremental Compilation

Importing a Lower-Level Partition Into the Top-Level Project119
Chapter 8: Simulation121
Simulating Designs with EDA Tools123
Specifying EDA Simulation Tool Settings124
Generating Simulation Output Files125
EDA Simulation Flow127
EDA Tool Functional Simulation Flow127
NativeLink Simulation Flow128
Manual Timing Simulation Flow128
Simulation Libraries129
Quartus I Simulator131
Creating Waveform Files133
Using the Simulator Tool134
Chapter 9: Timing Analysis137
Choosing the TimeQuest or Classic Timing Analyzer139
TimeQuest Timing Analysis139
Running the TimeQuest Timing Analyzer140
Tasks Pane141
Report Pane141
View Pane141
Classic Timing Analysis142
Specifying Classic Timing Requirements142
Specifying Project-Wide Classic Timing Settings144
Specifying Individual Timing Assignments145
Performing a Classic Timing Analysis147
Performing an Early Timing Estimate148
Classic Timing Analysis Reporting150
Making Assignments & Viewing Delay Paths151
Viewing Timing Delays with the Technology Map Viewer153
Performing Timing Analysis with EDA Tools155
Using the PrimeTime Software157
Using the Tau Software158
Chapter 10: Timing Closure159
Using the Chip Planner161
Chip Planner Tasks And Layers161
Making Assignments162

Simulating Designs with the

Achieve Timing Closure162
Using Netlist Optimizations to Achieve Timing Closure164
Preserve Timing167
Soft LogicLock Regions167
Path-Based Assignments167


Achieve Timing Closure169
Chapter 1: Power Analysis171
Power Analysis with the PowerPlay Power Analyzer172
Specifying Power Analyzer Options174
Using the PowerPlay Early Power Estimator176
Chapter 12: Programming & Configuration179
Programming One or More Devices WiththeProgrammer184
Creating Secondary Programming Files185
Creating Other Programming File Formats186
Converting Programming Files188
Using the QuartusII Software to ProgramViaa Remote JTAG Server192
Chapter 13: Debugging193
Using the SignalTap I Logic Analyzer195
Setting Up the SignalTapII Logic Analyzer196
Analyzing SignalTap I Data200
Using an External Logic Analyzer202
Using SignalProbe204
Using the In-System Memory Content Editor206
Using the In-System Sources and Probes Editor208
Using the RTL Viewer& Technology MapViewer For Debugging209
Chapter 14: Engineering Change Management211
Identifying Delays & Critical Paths WiththeChip Planner213
Editing Atoms in the Chip Planner214
Modifying Resource Properties With the Resource Property Editor215
Viewing & Managing Changes with the Change Manager217
Verifying ECO Changes219
Chapter 15: Formal Verification221
Using the Cadence Encounter Conformal Software223
Chapter 16: System-Level Design227
Creating SOPC Designs with SOPC Builder230
Creating the System230
Generating the System231
Creating DSP Designs with the DSP Builder232
Instantiating Functions233
Generating Simulation Files233
Generating Files for Synthesis233
Chapter 17: Installation, Licensing & Technical Support235
Installing the Quartus I Software236
Licensing the Quartus I Software237
Getting Technical Support239
Chapter 18: Documentation & Other Resources241
Getting Online Help242
Starting the Quartus I Interactive Tutorial244
Other Quartus I Software Documentation244
Other Altera Literature246


The Altera® Quartus®II design software is the most comprehensive environment available for system-on-a-programmable-chip (SOPC) design. This manual is designed for the novice QuartusII software user and provides an overview of the capabilities of the QuartusII software in programmable logic design. It is not, however, intended to be an exhaustive reference manual for the QuartusII software. Instead, it is a guide that explains the features of the software and how these can assist you in FPGA and CPLD design. This manual is organized into a series of specific programmable logic design tasks. Whether you use the QuartusII graphical user interface, other EDA tools, or the QuartusII command-line interface, this manual guides you through the features that are best suited to your design flow.

The first chapter gives an overview of the major graphical user interface, EDA tool, and command-line interface design flows. Each subsequent chapter begins with an introduction to the specific purpose of the chapter, and leads you through an overview of each task flow. It shows you how to integrate the QuartusII software with your existing EDA tool and command-line design flows. In addition, the manual refers you to other resources that are available to help you use the QuartusII software, such as QuartusII online Help and the QuartusII interactive tutorial, application notes, white papers, and other documents and resources that are available on the Altera website.

Use this manual to learn how the QuartusII software can help you increase productivity and shorten design cycles; integrate with existing programmable logic design flows; and achieve design, performance, and timing requirements quickly and efficiently.

Documentation Conventions

The Introduction to the QuartusII Software manual uses the following conventions to make it easy for you to find and interpret information.

Typographic Conventions

QuartusII documentation uses the typographic conventions shown in the following table:

Visual CueMeaning

Bold Initial Capitals

Command names; dialog box, page, and tab titles; and button names are shown in bold, with initial capital letters. For example: Find Text command, Save As dialog box, and Start button.

boldDirectory, project, disk drive , file names, file extensions, software utility and software executable names; file name extensions, and options in dialog boxes are shown in bold. Examples: quartus directory, d: drive, license.dat file.

Initial CapitalsKeyboard keys, user-editable application window fields, window names, view names, and menu names are shown with initial capital letters. For example: Delete key, the Options menu.

“Subheading Title”

Subheadings within a manual section are enclosed in quotation marks. In manuals, titles of Help topics are also shown in quotation marks.

Italic Initial Capitals

Help categories, manual titles, section titles in manuals, and application note and brief names are shown in italics with initial capital letters. For example: FLEXlm End Users Guide.

italicsVariables are enclosed in angle brackets (< >) and shown in italics. For example: <file name>, <DVD-ROM drive>.

Courier fontAnything that must be typed exactly as it appears is shown in Courier. For example: \quartus\bin\lmutil lmhostid.

rEnter or return key.

■Bullets are used in a list of items when the sequence of the items is not important.

fThe feet show you where to go for more information on a particular topic.

vThe checkmark indicates a procedure that consists of one step only.

!The hand points to information that requires special attention.


The following table shows terminology that is used throughout the Introduction to the QuartusII Software manual:

Term Meaning

“click”Indicates a quick press and release of the left mouse button. It also indicates that you need to use a mouse or key combination to start an action.

“double-click”Indicates two clicks in rapid succession.

“select”Indicates that you need to highlight text and/or objects or an option in a dialog box with a key combination or the mouse. A selection does not start an action. For example: Select Chain Description File, and then click OK.

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