Baixe Automation System S7-400 e outras Notas de estudo em PDF para Cultura, somente na Docsity! Preface, Contents Structure of a CPU 41x 1 Memory Concept and Startup Scenarios 2 Cycle and Reaction Times of the S7-400 3 Technical Specifications 4 Index Edition 12/2002 A5E00165965-01 Automation System S7-400 CPU Specifications Reference Manual SIMATIC This manual is part of the documentation package with the order number 6ES7398-8AA03-8BA0 Index-2 Automation System S7-400 A5E00165965-01 ! Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken. ! Warning indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken. ! Caution indicates that minor personal injury can result if proper precautions are not taken. Caution indicates that property damage can result if proper precautions are not taken. Notice draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation. Qualified Personnel Only qualified personnel should be allowed to install and work on this equipment. Qualified persons are defined as persons who are authorized to commission, to ground and to tag circuits, equipment, and systems in accordance with established safety practices and standards. Correct Usage Note the following: ! Warning This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended. Trademarks SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners. Safety Guidelines This manual contains notices intended to ensure personal safety, as well as to protect the products and connected equipment against damage. These notices are highlighted by the symbols shown below and graded according to severity by the following texts: We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed. Disclaim of LiabilityCopyright Siemens AG 2002 All rights reserved The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG Bereich Automation and Drives Geschaeftsgebiet Industrial Automation Systems Postfach 4848, D- 90327 Nuernberg Siemens AG 2002 Technical data subject to change. Siemens Aktiengesellschaft A5E000165965-01 Preface v Automation System S7-400 CPU Specifications A5E00165965-01 Note In order to program and commission an S7-400 you require STEP 7 V52 as well as the following manuals or manual packages: Manual/ Manual Package Chapter Overview Standard Software for S7 and M7 STEP 7 Basic Information • Installing and starting up STEP 7 on a programming device / PC • Working with STEP 7 with the following contents: Managing projects and files Configuring and assigning parameters to the S7-400 configuration Assigning symbolic names for user programs Creating and testing a user program in STL/LAD Creating data blocks Configuring the communication between two or more CPUs Loading, storing and deleting user programs in the CPU / programming device Monitoring and controlling user programs Monitoring and controlling the CPU • Guide for efficiently implementing the programming task with the programming device / PC and STEP 7 • How the CPUs work (for example, memory concept, access to inputs and outputs, addressing, blocks, data management) • Description of STEP 7 data management • Using data types of STEP 7 • Using linear and structured programming • Using block call instructions • Using the debug and diagnostic functions of the CPUs in the user program (for example, error OBs, status word) STEP 7 Reference Information Statement List (STL) for S7-300 and S7-400 Ladder Logic (LAD) • Basic procedure for working with STL, LAD, or FBD (for example, structure of STL, LAD, or FBD, number formats, syntax) • Description of all instructions in STEP 7 (with program examples) • Description of the various addressing methods in STEP 7 (with examples) • Description of all functions integrated in the CPUs • Description of the internal registers in the CPUfor S7-300 and S7-400 Function Block Diagram (FBD) for S7-300 and S7-400 System and Standard Functions • Description of all system functions integrated in the CPUs • Description of all organization blocks integrated in the CPUs Manual PG 7xx • Description of the programming device hardware • Connecting a programming device to various devices • Starting up a programming device Preface vi Automation System S7-400 CPU Specifications A5E00165965-01 Recycling and Disposal The S7-400 is low in contaminants and can therefore be recycled. To recycle and dispose of your old device in an environment-friendly manner, please contact a disposal company certified for disposal of electronic waste. Further Support If you have any technical questions, please get in touch with your Siemens representative or agent responsible. http://www.siemens.com/automation/partner Training Centers We offer a number of courses to help you become familiar with the SIMATIC S7 programmable logic controller. Please contact your regional training center or our central training center in D 90327 Nuremberg, Germany for details: Phone: +49 (911) 895-3200. Internet: http://www.sitrain.com Preface vii Automation System S7-400 CPU Specifications A5E00165965-01 A&D Technical Support Available 24 hours a day, worldwide: Johnson City Nuremberg Bejiing Technical Support Worldwide (Nuremberg) Technical Support Local time: 0:00 to 24:00 / 365 days Phone: +49 (0) 180 5050-222 Fax: +49 (0) 180 5050-223 E-Mail: adsupport@ siemens.com GMT: +1:00 Europe / Africa (Nuremberg) Authorization Local time: Mo. - Fr. 8:00 am to 5:00 pm Phone: +49 (0) 180 5050–222 Fax: +49 (0) 180 5050-223 E-Mail: adsupport@ siemens.com GMT: +1:00 United States (Johnson City) Technical Support and Authorization Local time: Mo. - Fr. 8:00 am to 5:00 pm Phone: +1 (0) 423 262 2522 Fax: +1 (0) 423 262 22 89 E-mail: simatic.hotline@ sea.siemens.com GMT: –5:00 Asia / Australia (Bejiing) Technical Support and Authorization Local time: Mo. - Fr. 8:00 am to 5:00 pm Phone: +86 10 64 75 75 75 Fax: +86 10 64 74 74 74 E-mail: adsupport.asia@ siemens.com GMT: +8:00 The languages of the SIMATIC Hotlines and the authorization hotline are generally German and English. Contents x Automation System S7-400 CPU Specifications A5E00165965-01 3 Cycle and Reaction Times of the S7-400 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Cycle Time 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Cycle Time Calculation 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Different Cycle Times 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Communication Load 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Reaction Time 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 How Cycle and Reaction Times Are Calculated 3-18. . . . . . . . . . . . . . . . . . . . . . 3.7 Examples of Calculating the Cycle Time and Reaction Time 3-19. . . . . . . . . . . 3.8 Interrupt Reaction Time 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Example of Calculating the Interrupt Reaction Time 3-24. . . . . . . . . . . . . . . . . . 3.10 Reproducibility of Time-Delay and Watchdog Interrupts 3-25. . . . . . . . . . . . . . . 4 Technical Specifications 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Technical Specifications of the CPU 412-1; (6ES7412-1XF03-0AB0) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Technical Specifications of the CPU 412-2; (6ES7412-2XG00-0AB0) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Technical Specifications of the CPU 414-2; (6ES7414-2XG03-0AB0) 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Technical Specifications of the CPU 414-3; (6ES7414-3XJ00-0AB0) 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Technical Specifications of the CPU 416-2; (6ES7416-2XK02-0AB0, 6ES7416-2FK02-0AB0) 4-18. . . . . . . . . . . . . . . . . . . . 4.6 Technical Specifications of the CPU 416-3; (6ES7416-3XL00-0AB0) 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Technical Specifications of the CPU 417-4; (6ES7417-4XL00-0AB0) 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Technical Specifications of the Memory Cards 4-30. . . . . . . . . . . . . . . . . . . . . . . Index Index-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents xi Automation System S7-400 CPU Specifications A5E00165965-01 Figures 1-1 Layout of the Controls and Indicators of the CPU 412-1 1-2. . . . . . . . . . . . . . 1-2 Layout of the Controls and Indicators of the CPU 41x-2 1-3. . . . . . . . . . . . . . . 1-3 Layout of the Controls and Indicators of the CPU 41x-3 1-4. . . . . . . . . . . . . . . 1-4 Layout of the Controls and Indicators of the CPU 417-4 1-5. . . . . . . . . . . . . . 1-5 Positions of the Mode Selector 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Structure of the Memory Card 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Multicomputing Example 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Overview: Architecture enabling modification of a system during operation 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Diagnostics with CPU 41x 1-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Diagnostic Addresses for the DP Master and DP Slave 1-44. . . . . . . . . . . . . . . 1-11 Intermediate Memory in the CPU 41x as DP Slave 1-47. . . . . . . . . . . . . . . . . . . 1-12 Diagnostic Addresses for the DP Master and DP Slave 1-54. . . . . . . . . . . . . . . 1-13 Structure of the Slave Diagnosis 1-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Structure of the Module Diagnosis of the CPU 41x 1-60. . . . . . . . . . . . . . . . . . . 1-15 Structure of the Station Diagnosis 1-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Bytes +4 to +7 for Diagnostic and Process Interrupts 1-62. . . . . . . . . . . . . . . . . 1-17 Direct Communication with CPUs 41x 1-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Diagnostic Address for the Recipient During Direct Communication 1-66. . . . 3-1 Parts and Composition of the Cycle Time 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Different Cycle Times 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Minimum Cycle Time 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Formula: Influence of Communication Load 3-10. . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Breakdown of a Time Slice 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Dependency of the Cycle Time on the Communication Load 3-12. . . . . . . . . . 3-7 DP Cycle Times on the PROFIBUS-DP Network 3-14. . . . . . . . . . . . . . . . . . . . . 3-8 Shortest Reaction Time 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Longest Reaction Time 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Calculating the Interrupt Reaction Time 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents xii Automation System S7-400 CPU Specifications A5E00165965-01 Tables 1-1 LEDs of the CPUs 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Positions of the Mode Selector 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Protection Levels of a S7-400 CPU 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Types of Memory Cards 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CPUs 41x (MPI/DP Interface as PROFIBUS DP) 1-35. . . . . . . . . . . . . . . . . . . 1-6 CPUs 41x (MPI/DP Interface and DP Module as PROFIBUS DP) 1-35. . . . . . 1-7 Meaning of the BUSF LED of the CPU 41x as DP Master 1-41. . . . . . . . . . . . . 1-8 Reading Out the Diagnosis with STEP 7 1-42. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Event Detection of the CPUs 41x as DP Master 1-45. . . . . . . . . . . . . . . . . . . . . 1-10 Configuration Example for the Address Areas of the Intermediate Memory 1-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Meaning of the BUSF LEDs of the CPU 41x as DP Slave 1-51. . . . . . . . . . . . . 1-12 Reading Out the Diagnostic Data with STEP 5 and STEP 7 in the Master System 1-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Event Detection of the CPUs 41x as DP Slave 1-55. . . . . . . . . . . . . . . . . . . . . . 1-14 Evaluation of RUN-STOP Transitions in the DP Master/DP Slave 1-55. . . . . 1-15 Structure of the Station Status 1 (Byte 0) 1-57. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Structure of Station Status 2 (Byte 1) 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Structure of Station Status 3 (Byte 2) 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Structure of the Master PROFIBUS Address (Byte 3) 1-58. . . . . . . . . . . . . . . . 1-19 Structure of the Manufacturer ID (Bytes 4, 5) 1-59. . . . . . . . . . . . . . . . . . . . . . . . 1-20 Event Detection of the CPUs 41x as Recipient During Direct Communication 1-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Evaluation of the Station Failure in the Sender During Direct Communication 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Memory Requirements 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Cyclic Program Scanning 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Factors that Influence the Cycle Time 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Portions of the process image transfer time 3-5. . . . . . . . . . . . . . . . . . . . . . . . 3-4 Portions of the process image transfer time, H CPUs 3-6. . . . . . . . . . . . . . . . 3-5 User program processing time for the CPU 41x-4H 3-7. . . . . . . . . . . . . . . . . . 3-6 Operating system scan time at scan cycle checkpoint 3-7. . . . . . . . . . . . . . . . 3-7 Increase in Cycle Time by Nesting Interrupts 3-7. . . . . . . . . . . . . . . . . . . . . . . . 3-8 Reducing the Reaction Time 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Example of Calculating the Reaction Time 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Hardware Interrupt and Diagnostic Interrupt Reaction Times; Maximum Interrupt Reaction Time Without Communication 3-22. . . . . . . . . . . 3-11 Reproducibility of Time-Delay and Watchdog Interrupts of the CPUs. 3-25. . Structure of a CPU 41x 1-3 Automation System S7-400 CPU Specifications A5E00165965-01 Controls and Indicators of the CPU 41x-2 Mode selector Slot for the memory card Incoming supply of Under cover LEDs INTF, EXTF, BUS1F, BUS2F, FRCE, RUN, STOP MPI/PROFIBUS DP interface PROFIBUS DP interface BUS1F BUS2F CPU 414-2 6ES7414-2XG03-0AB0 Module designation, version, abbre- viated order number and firmware version V3.0.0 external backup voltage Figure 1-2 Layout of the Controls and Indicators of the CPU 41x-2 Structure of a CPU 41x 1-4 Automation System S7-400 CPU Specifications A5E00165965-01 Controls and Indicators of the CPU 41x-3 Mode selector Slot for the memory card Under coverUnder cover Module slot for in- terface module LEDs INTF, EXTF, BUS1F, BUS2F, FRCE, RUN, STOP MPI/PROFIBUS DP interface PROFIBUS DP interface LEDs IFM1F BUS1F BUS2F IFM1F CPU 416-3 6ES7416-3XL00-0AB0 Module designation, version, abbre- viated order number and firmware version V3.0.0 Incoming supply of external backup voltage Figure 1-3 Layout of the Controls and Indicators of the CPU 41x-3 Structure of a CPU 41x 1-5 Automation System S7-400 CPU Specifications A5E00165965-01 Controls and Indicators of the CPU 417-4 Mode selector Slot for the memory card Under coverUnder cover Module slot for in- terface module 1 Module slot for in- terface module 2 LEDs INTF, EXTF, BUS1F, BUS2F, FRCE, RUN, STOP MPI/PROFIBUS DP interface PROFIBUS DP interface LEDs IFM1F, IFM2F BUS1F BUS2F IFM1F IFM2F Under the metal lid on the left-hand side Interface for memory expansion Module designation, version, abbre- viated order number and firmware version V3.0.0 Incoming supply of external backup voltage Figure 1-4 Layout of the Controls and Indicators of the CPU 417-4 LEDs Table 1-1 gives you an overview of the LEDs on the individual CPUs. Section 1.2 describes the states and errors indicated by these LEDs. Structure of a CPU 41x 1-8 Automation System S7-400 CPU Specifications A5E00165965-01 Incoming Supply of External Backup Voltage at the “EXT.-BATT.” Socket You can use one or two backup batteries – depending on the module type – in the power supply modules of the S7-400 to do the following: • Provide backup power for the user program you have stored in RAM. • Maintain memory bits, times, counts and system data as well as data in variable data blocks. • Provide backup power for the internal clock. You can achieve the same backup power by connecting a voltage between 5 V and 15 V DC to the “EXT.-BATT.” socket of the CPU. The “EXT.-BATT.” input has the following features: • Reverse polarity protection • A short-circuit current limit of 20 mA You need a cable with a 2.5 mm ∅ jack to connect power to the “EXT.-BATT” socket, as shown in the following illustration. Note the polarity of the jack. Positive pole Negative pole 2.5 mm jack ∅ Note You will require the external incoming supply at the “EXT.-BATT.” socket if you replace a power supply module and want to provide a backup supply for the user program stored in RAM and the data mentioned above while the module is being replaced. Structure of a CPU 41x 1-9 Automation System S7-400 CPU Specifications A5E00165965-01 1.2 Monitoring Functions of the CPU Monitoring and Error Messages The CPU hardware and the operating system have monitoring functions that ensure that the system functions correctly and that there is a defined response in the event of an error. A number of errors will also produce a response from the user program. The following table gives you an overview of possible errors, their causes and the responses of the CPU. Type of Fault/Error Cause of Fault Response of the Operating System Error LED Clock pulse failure Monitoring of the failure of the processor clock pulse System standstill Disabling of the digital outputs by issuing the “OD” (Output Disable) signal – Access error Module failure (SM, FM, CP) ”EXTF” LED lights up until the fault is acknowledged. In SMs: • OB 122 call • Entry in the diagnostic buffer • In the case of input modules: Entry of null for the date in the accumulator or the process image In the case of other modules: • OB 122 call EXTF Clock synchronous interrupt Start a program synchronized to the DP clock Call OB 61 to OB 64 – Timing error • The runtime of the user program (OB1 and all the interrupts and error OBs) exceeds the specified maximum cycle time. • OB request error • Overrun of the start information buffer • Time error interrupt • Re-enter RUN following CiR ”INTF” LED lights up until the fault is acknowledged. OB 80 call If the OB is not loaded: The CPU goes into STOP mode. INTF Power supply module error (not power failure) In the central or distributed I/O rack: • At least one backup battery in the power supply module is empty. • The backup voltage is missing. • The 24 V supply to the power supply module has failed. OB 81 call If the OB is not loaded: The CPU continues to run. EXTF Diagnostic Interrupt An I/O module with interrupt capability reports a diagnostic interrupt. OB 82 call If the OB is not loaded: The CPU goes into STOP mode. EXTF Remove/insert interrupt Removal or insertion of an SM and insertion of an incorrect module type. The LED EXTF will not light up if the only inserted SM is removed from the CPU in STOP during default configuration. The LED lights up briefly when the SM is inserted again. OB 83 call If the OB is not loaded: The CPU goes into STOP mode. EXTF Structure of a CPU 41x 1-10 Automation System S7-400 CPU Specifications A5E00165965-01 Type of Fault/Error Error LED Response of the Operating System Cause of Fault Priority class error • Priority class is called, but the corresponding OB is not available. • In the case of an SFB call: The instance DB is missing or defective. OB 85 call If the OB is not loaded: The CPU goes into STOP mode. INTF • Error during the updating of the process image EXTF Failure of a rack/station • Power failure in an expansion rack • Failure of a DP line • Failure of a coupling line: missing or defective IM, interrupted line) OB 86 call If the OB is not loaded: The CPU goes into STOP mode. EXTF Communication error • Status information cannot be entered in DB • Incorrect frame identifier • Frame length error • Error in the structure of the global data message • DB access error OB 87 call If the OB is not loaded: The CPU goes into STOP mode. INTF Cancel processing • Nesting depth exceeded for synchronous errors • Too many nested block calls (B stack) • Error allocating local data Call OB 88 If the OB is not loaded: The CPU goes into STOP mode. INTF Programming error Error in the machine code or in the user program: • BCD conversion error • Range length error • Range error • Alignment error • Write error • Timer number error • Counter number error • Block number error • Block not loaded OB 121 call If the OB is not loaded: The CPU goes into STOP mode. INTF MC7 code error Error in the compiled user program (e.g. impermissible OP code or jump over the end of the block) CPU goes into STOP mode. Reboot or memory reset required. INTF Loss of clock Clock was lost either because an OB 61 to 64 was not start due to higher priorities or because additional asynchronous bus loads suppressed the bus clock. Call OB 61..64 at the next pulse. INTF EXTF There are also test and information functions available in each CPU that you can call up with STEP 7. Structure of a CPU 41x 1-13 Automation System S7-400 CPU Specifications A5E00165965-01 Error LEDs and Points to Note, CPU 41x-3 and 41x-4 The CPUs 41x-3 and 41x-4 continue to have the LED IFM1F and LEDs IFM1F and IFM2F. These indicate errors in connection with the first and second module interfaces. LED Meaning IFM1F IFM2F H x An error has been detected at module interface 1. x H An error has been detected at module interface 2. B x DP master: One or more slaves on the PROFIBUS DP interface module inserted in module slot 1 are not responding DP slave: not addressed by the DP master x B DP master: One or more slaves on the PROFIBUS DP interface module inserted in module slot 2 are not responding DP slave: not addressed by the DP master H = LED lights up; B = LED flashes; x = LED status is irrelevant Diagnostic buffer You can read out the exact cause of an error in STEP 7 (PLC –> Module Information) from the diagnostic buffer. Structure of a CPU 41x 1-14 Automation System S7-400 CPU Specifications A5E00165965-01 1.4 Mode Selector Function of the Mode Selector Using the mode selector, you can put the CPU in RUN/RUN-P or STOP mode or reset the memory of the CPU. STEP 7 offers further options for changing the mode. Positions The mode selector switch is designed as a keyswitch. Figure 1-5 illustrates the possible positions of the mode selector. RUN-P RUN STOP MRES Figure 1-5 Positions of the Mode Selector Table 1-2 explains the positions of the mode selector. In the event of a fault or if there are startup problems, the CPU will go into or remain in STOP mode irrespective of the position of the mode selector. Structure of a CPU 41x 1-15 Automation System S7-400 CPU Specifications A5E00165965-01 Table 1-2 Positions of the Mode Selector Position Explanation RUN-P If there is no startup problem or error and the CPU can go into RUN, the CPU processes the user program or is idle. It is possible to access the I/O. The key cannot be removed in this position. Programs can: • Be read out with the programming device from the CPU (CPU programming device) • Be transferred to the CPU (programming device CPU). RUN If there is no startup problem or error and the CPU can go into RUN, the CPU processes the user program or runs in idle. It is possible to access the I/O. The key can be removed in this position to ensure that the mode cannot be changed without authorization. The programming device can read the programs in the CPU (CPU –> PG). The program in the CPU cannot be changed when the switch is in the RUN position (see STEP 7)! The protection level can be bypassed using a password set in the STEP 7 / Hardware Configuration (STEP 7 V4.02 and above). In other words, if you use this password, the program can also be changed when the switch is in the RUN position. STOP The CPU does not process the user program. The digital signal modules are disabled. The key can be removed in this position to ensure that the operating mode cannot be changed without authorization. Programs can: • Be read out with the programming device from the CPU (CPU programming device) • Be transferred to the CPU (programming device CPU). MRES (Master Reset) Momentary-contact position of the key switch for the master reset of the CPU and for cold restart (see the following pages). Protection Levels A protection level can be defined in the CPUs of the S7-400 that can be used to protect the programs in the CPU from unauthorized access. You can determine with the protection level which programming device functions a user can execute on the CPU in question without particular authorization (password). You can execute all the programming device functions using a password. Setting the Protection Levels You can set the protection levels (1 to 3) for a CPU under STEP 7/Configuring Hardware. You can remove the protection level set under STEP 7/Configuring Hardware using a manual reset with the mode selector. You can also set protection levels 1 and 2 using the mode selector. Table 1-3 lists the protection levels of a CPU of the S7-400. Structure of a CPU 41x 1-18 Automation System S7-400 CPU Specifications A5E00165965-01 1.5 Design and Function of Memory Cards Order Numbers The order numbers for memory cards are listed in the technical specifications in Chapter 4. Configuration The memory card is slightly larger than a credit card and protected by a strong metal casing. It is plugged into a receptacle at the front of the CPU; the end to be inserted is obvious from the design of the memory card. Grip Side elevation Type plate Front elevation O rd er n um be r N am e of th e M em or y C ar d Figure 1-6 Structure of the Memory Card Function The memory card and an integrated memory area on the CPU together form the load memory of the CPU. In operation, the load memory contains the complete user program including comments, symbols, special additional information that permits decompiling of the user program, and all the module parameters (see Chapter 2.1). Structure of a CPU 41x 1-19 Automation System S7-400 CPU Specifications A5E00165965-01 What the Memory Card Contains The following data can be stored in the memory card: • User program, that is, blocks (OBs, FBs, FCs, DBs) and system data • Parameters that determine the behavior of the CPU • Parameters that determine the behavior of the I/O modules. • As of STEP 7 V5.1 the Project in Their Entirety in Suitable Memory Cards. Types of Memory Cards for the S7-400 Two types of memory card are used in the S7-400: • RAM cards • Flash cards (FEPROM cards) Note Non-Siemens memory cards cannot be used in the S7-400. What Type of Memory Card Should You Use? Whether you use a RAM card or a Flash card depends on how you intend to use the memory card. Table 1-4 Types of Memory Cards If you ... ...Then want to store the data in RAM and you want to modify your program during RUN or RUN-P mode, use a RAM card want to store your user program permanently on the memory card, even with power removed (without backup or outside the CPU), use a Flash card Structure of a CPU 41x 1-20 Automation System S7-400 CPU Specifications A5E00165965-01 RAM Card you use a RAM card, you must plug this into the CPU to load the user program. The user program is loaded with the help of the programming device (PG). You can load the entire user program or the individual parts such as FBs, FCs, OBs, DBs, or SDBs into the load memory in STOP mode or in RUN-P mode. If you remove the RAM card from the CPU, the information stored on it is lost. The RAM card does not have a built-in backup battery. If the power supply has a functioning backup battery or if an external backup voltage is supplied to the CPU via the “EXT. BATT.” socket, the contents of the RAM card are retained after switching off the power supply provided the RAM card remains plugged into the CPU and the CPU remains in the rack. Flash Card If you use a Flash card, there are two ways of loading the user program: • Set the CPU to STOP with the mode selector, plug the Flash card into the CPU, and load the user program with STEP 7 “PLC –> Load User Program to Memory Card”. • Load the user program into the Flash card in offline mode at the programming device or adapter and then insert the Flash card into the CPU. You can only load your complete user program with the Flash card. You can load smaller program sections into the integrated load memory on the CPU using the programming device. In the case of larger program changes, you must always reload the Flash card with the complete user program. The Flash card does not require voltage to store its contents, that is, the information stored on it is retained even when you remove the Flash card from the CPU or if you operate your S7-400 system without backup (without backup battery in the power supply module or “EXT. BATT.” socket of the CPU). Which Memory Card Capacity to Use The capacity of the memory card you use depends on the size of the user program and the additional memory requirement resulting from the use of function modules or communications modules. See the manuals of these modules for details of their memory requirements. To optimally use the working memory (code and data) your CPU, you should expand the load memory of the CPU with a memory card with at least the same capacity as the working memory. Structure of a CPU 41x 1-23 Automation System S7-400 CPU Specifications A5E00165965-01 Multipoint Interface as DP Interface You can also configure the MPI interface as a DP interface. To do this, you can reconfigure the MPI interface under STEP 7 in SIMATIC Manager. You can use this to set up a DP line with a maximum of 32 slaves. 1.7 PROFIBUS DP Interface Connectable Devices You can connect any PROFIBUS DP slave that complies with the standard to the PROFIBUS DP interface. In this case, the CPU is either a DP master or DP slave connected via the PROFIBUS DP field bus to the passive slave stations or other DP masters. Some connectable devices take a supply of 24 V from the interface. This voltage is available there in non-isolated form. Connector Use only the bus connector for PROFIBUS DP or PROFIBUS cable for connecting devices to the PROFIBUS DP interface (see Chapter 7 in the Installation Manual). Structure of a CPU 41x 1-24 Automation System S7-400 CPU Specifications A5E00165965-01 1.8 Overview of the Parameters for the S7-400 CPUs Default Values All the parameters have default settings at delivery. These defaults, which are suitable for a whole range of standard applications, mean that the S7-400 can be used immediately without the need for further settings. You can find the CPU-specific default values using “Configuring Hardware” in STEP 7. Parameter Blocks The behavior and properties of the CPU are defined using parameters that are stored in system data blocks. The CPUs have a defined default setting. You can change this default setting by modifying the parameters in the hardware configuration. The following list gives you an overview of the configurable system properties available in the CPUs. • General properties (e.g. Name of the CPU) • Startup (e.g. enabling of a restart) • Clock synchronous interrupts • Cycle/clock memory (e.g. cycle monitoring time) • Retentivity (number of memory markers, timers and counters that are maintained) • Memory (e.g.local data) Note: If, for example, you set greater or smaller values than the default values for the process image, the number of diagnostic buffer entries and the maximum number of ALARM-8 blocks (SFB 34 and SFB 35) and blocks for S7 communication, the working memory available for the program code and for data blocks will be reduced or increased by this amount. • Assignment of interrupts (process interrupts, delay interrupts, asynchronous error interrupts) to the priority classes • Time-of-day interrupts (e.g. start, interval duration, priority) • Watchdog interrupts (e.g. priority, interval duration) • Diagnostics/clock (e.g. time synchronization) • Protection levels Note 16 memory bytes and 8 counter numbers are set to retentive in the default settings, in other words, they are not deleted when the CPU is restarted. Structure of a CPU 41x 1-25 Automation System S7-400 CPU Specifications A5E00165965-01 Parameter Assignment Tool You can set the individual CPU parameters using “Configuring Hardware” in STEP 7. Note If you make changes to the existing settings of the following parameters, the operating system carries out initializations like those during cold restart. • Size of the process image of the inputs • Size of the process image of the inputs • Size of the local data • Number of diagnostic buffer inputs • Communication resources These initializations are: – Data blocks are initialized with the load values – Memory bits, times, counts, inputs and outputs are deleted regardless of the retentive settings (0) – DBs generated via SFC are deleted – Permanently configured, base communication connections are established – All the priority classes start from the beginning again Structure of a CPU 41x 1-28 Automation System S7-400 CPU Specifications A5E00165965-01 1.9.1 Peculiarities Slot Rules In multicomputing operation, up to four CPUs can be inserted at the same time in a central controller (CC) in any order. If you use CPUs that can only handle module start addresses that are divisible by 4 (usually CPUs before 10/98), you must keep to this rule for all the configured CPUs when you assign addresses! The rule applies should you also use CPUs that allow the bytewise assignment of module start addresses in single-computing operation. Bus Connection The CPUs are connected to one another via the communication bus (K bus). In other words, if configured appropriately, all the CPUs can be reached by the programming device via an MPI interface. Behavior at Startup and During Operation At startup, the CPUs involved in multicomputing operation automatically check whether they can synchronize with each other. Synchronization is only possible if: • All the configured CPUs (but only those) are inserted and not defective. • Correct configuration data (SDBs) have been created and loaded for all the inserted CPUs. If one of these prerequisites is not met, the event is entered in the diagnostic buffer with ID 0x49A4. You can find explanations of the event IDs in the reference information for standard and system functions. When STOP mode is exited, a comparison of the types of startup (COLD RESTART/REBOOT (WARM RESTART/RESTART) is carried out. If their startup type differs, the CPUs do not go into RUN mode. Assignment of Addresses and Interrupts In multicomputing operation, the individual CPUs can each access the modules that were allocated to them during configuration with STEP 7. The address area of a module is always assigned exclusively to a CPU. Each interrupt-capable module is assigned to a CPU. Interrupts originating from such a module cannot be received by the other CPUs. Structure of a CPU 41x 1-29 Automation System S7-400 CPU Specifications A5E00165965-01 Interrupt Processing The following applies to interrupt processing: • Process interrupts and diagnostic interrupts are only sent to one CPU. • When a module fails or is removed or inserted, the interrupt is processed by the CPU that was assigned to the module at parameter assignment with STEP 7. Exception: A module insertion/removal interrupt that starts from a CP reaches all the CPUs even if the CP was assigned to a CPU at configuration with STEP 7. • In the event of a rack failure, OB 86 is called on each CPU, including CPUs that were not assigned a module in the failed rack. You can find further information on the OB 86 in the reference information on organization blocks. Typical I/O Application Specification The typical I/O application specification of a programmable controller corresponds in multicomputing operation to the typical application specification of the CPU with the most resources. The relevant CPU-specific or DP master-specific typical application specifications cannot be exceeded in the individual CPUs. 1.9.2 Multicomputing Interrupt Using the multicomputing interrupt (OB 60), you can respond synchronously to an event in multicomputing on the corresponding CPUs. In contrast to the process interrupts triggered by signal modules, the multicomputing interrupt can be output only by CPUs. The multicomputing interrupt is triggered by calling SFC 35 “MP_ALM“. You will find more information in the System Software for S7-300/400, System and Standard Functions manual. 1.9.3 Configuring and Programming Multicomputing Operation Please refer to the manual Configuring Hardware and Communication Connections with STEP 7 V5.2 to find out how to configure and program the CPUs and the modules. Structure of a CPU 41x 1-30 Automation System S7-400 CPU Specifications A5E00165965-01 1.10 Modifications to the System During Operation The ability to modify the system during operation using CiR (Configuration in RUN) allows you to make certain changes to the configuration in the RUN mode. Processing is halted for a brief period in order to accomplish this. The upper limit of this time period is set to one second by default but can be changed. During this time, the process inputs retain their most recent value (see the manual, “ Modifications to the System During Operation Using CiR” You can download a free copy of this manual from the Internet address:http://www.siemens.com/automation/service&support You can modify the system during operation using CiR in system segments with distributed I/O. This requires a configuration as shown in the following illustration. To simplify the example, only one DP master system and one PA master system are shown. These restrictions do not apply in actual practice. ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Modular DP Slave ET200M, ET200S or ET200iS Compact DP Slave IM 157+ DP/PA Coupler PA Slave (field device) SUBNET: PA Master System ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉDP Master MPI/DP interface of a CPU 41x or DP interface of a CPU 41x-2 or interface module IF 964-DP or an external DP interface module CP 443-5 ext. PROFIBUS: DP Master System PA Link PA Slave (field de- vice) Figure 1-8 Overview: Architecture enabling modification of a system during operation Structure of a CPU 41x 1-33 Automation System S7-400 CPU Specifications A5E00165965-01 Note If you wish to add or remove slaves or modules or make changes to an existing assignment to a process image partition, you can only do so on a maximum of four DP master systems. Any other changes during to the system operation that are not expressly listed above are not allowed and are not included in the this documentation. Structure of a CPU 41x 1-34 Automation System S7-400 CPU Specifications A5E00165965-01 1.11 CPU 41x as DP Master/DP Slave Introduction This section contains the properties and technical specifications for the CPUs 412-1, 412-2, 414-2, 414-3, 416-2, 416-3 and 417-4 that you will require if you want to use the CPU as a DP master or as a DP slave and configure them for direct communication. Clarification: Because DP master/DP slave behavior is the same for all CPUs, the CPUs are described as CPU 41x below. Note This description applies to CPUs as of V 3.1. Further References You can find descriptions of and information on configuration as a whole, the configuration of a PROFIBUS subnetwork and diagnostics in the PROFIBUS subnetwork in the STEP 7 online help system. Structure of a CPU 41x 1-35 Automation System S7-400 CPU Specifications A5E00165965-01 1.11.1 DP Address Areas of the CPUs 41x Address Areas of the CPUs 41x Table 1-5 CPUs 41x (MPI/DP Interface as PROFIBUS DP) Address Area 412-1 412-2 414-2 416-2 MPI interface as PROFIBUS DP, inputs and outputs (bytes) in each case 2048 2048 2048 2048 DP interface as PROFIBUS DP, inputs and outputs (bytes) in each case – 4096 6144 8192 In the process image, inputs and outputs in each case Can be set up to x bytes 4096 4096 8192 16384 Table 1-6 CPUs 41x (MPI/DP Interface and DP Module as PROFIBUS DP) Address area 414-3 416-3 417-4 MPI interface as PROFIBUS DP, inputs and outputs (bytes) in each case 2048 2048 2048 DP interface as PROFIBUS DP, inputs and outputs (bytes) in each case 6144 8192 8192 DP module as PROFIBUS DP, inputs and outputs (bytes) in each case 6144 8192 8192 In the process image, inputs and outputs in each case Can be set up to x bytes 8192 16384 16384 DP diagnostic addresses occupy at least one byte for the DP master and each DP slave in the address area. The DP standard diagnosis for each node can be called at these addresses, for example (LADDR parameter of SFC 13). You specify the DP diagnostic addresses during configuration. If you do not specify any DP diagnostic addresses, STEP 7 assigns the addresses from the highest byte address downwards as DP diagnostic addresses. In DPV1 mode of the master, the slaves generally have two diagnostic addresses. Structure of a CPU 41x 1-38 Automation System S7-400 CPU Specifications A5E00165965-01 Further Information You can find descriptions and information on changing from PROFIBUS DP to PROFIBUS DPV1 on the Internet at the following address: http://www.siemens.com/automation/service&support Under the item number 7027576 Monitor/Modify, Programming via PROFIBUS As an alternative to the MPI interface, you can use the PROFIBUS DP interface to program the CPU or execute the programming device functions Monitor and Modify. Note The applications Programming and Monitor/Modify via the PROFIBUS DP interface extend the DP cycle. Equidistance Equidistance is the property of the PROFIBUS DP that guarantees bus cycles of exactly identical length. “Identical length bus cycles” means that the DP master always begins the DP bus cycle after the same time interval. From the view of the slaves, this means that they receive their data from the master at the exact same time intervals. As of STEP7 V 5.2, you can configure equidistant bus cycles for PROFIBUS subnetworks. Consistent data Data that belongs together in terms of its content and a process state written at a specific point in time is known as consistent data.. To maintain consistency, the data should not be changed or updated during processing or transmission. A detailed description is available in Chapter 1.13. Structure of a CPU 41x 1-39 Automation System S7-400 CPU Specifications A5E00165965-01 SYNC/FREEZE With the SYNC control command, the DP slaves of the selected groups are switched to the Sync mode. In other words, the DP master transfers the current output data and instructs the DP slaves involved to freeze their outputs. With the following output frames, the DP slaves enter the output data in an internal buffer and the state of the outputs remains unchanged. Following each SYNC control command, the DP slaves of the selected groups apply the output data of their internal buffer to the outputs to the process. The outputs are only updated cyclically again when you send the UNSYNC control command using SFC 11 “DPSYC_FR”. With the FREEZE control command, the DP slaves involved are switched to the Freeze mode, in other words the DP master instructs the DP slaves to freeze the current state of the inputs. It then transfers the frozen data to the input area of the CPU.. Following each FREEZE control command, the DP slaves freeze the state of their inputs again. The DP master only receives the current state of the inputs cyclically again after you have sent the UNFREEZE control command with SFC 11 “DPSYC_FR”. Power-Up of the DP Master System Use the following parameters to set power-up monitoring of the DP master: • Transfer of the Parameters to Modules • ”Finished” Message by Means of Modules In other words, the DP slaves must power up and be configured by the CPU (as DP master) in the set time. PROFIBUS Address of the DP Master All PROFIBUS addresses are permissible. Structure of a CPU 41x 1-40 Automation System S7-400 CPU Specifications A5E00165965-01 1.11.3 Isochrone Updating of the Process Image Partition With SFC 126 “SYNC_PI“ you can update a process image partition of the inputs synchronous to the clock. A user program linked to a DP cycle can use this SFC to consistently and synchronously update input data located in a process image partition. SFC 126 can be interrupted and can only be called in OBs 61, 62, 63 and 64. With SFC 127 “SYNC_PO“ you can update a process image partition of the outputs synchronous to the clock. A user program linked to a DP cycle can use this SFC to synchronously update output data located in a process image partition and consistently transmit them to I/O devices. SFC 127 can be interrupted and can only be called in OBs 61, 62, 63 and 64. To be able to update process image partitions synchronous to the clock, all input or output addresses of a slaves must be assigned to the same process image partition. To ensure the consistency in a process image partition during each cycle, the following requirements must be fulfilled for each CPUs: • CPU 412: number of slaves + number of bytes / 100 < 10 • CPU 414: number of slaves + number of bytes / 50 < 20 • CPU 416: number of slaves + number of bytes / 50 < 26 • CPU 417: number of slaves + number of bytes / 50 < 20 SFC 126 and 127 are documented in the corresponding online help and in the manual “System and Standard Functions”. Structure of a CPU 41x 1-43 Automation System S7-400 CPU Specifications A5E00165965-01 Evaluating the Diagnosis in the User Program The following figure shows you how to evaluate the diagnosis in the user program. Diagnostic event Read out OB82_MDL_ADDR and Read out OB82_IO_FLAG (= input/output module identifier) For the diagnosis of the whole DP slave: Call SFC 13 Enter the diagnostic address OB82_MDL_ADDR* in the LADDR parameter Enter bit 0 of the OB82_IO_Flag as bit 15 in OB82_MDL_ADDR Result: Diagnostic address ”OB82_MDL_ADDR*” For the diagnosis of the relevant modules: Call SFC 51 Enter the diagnostic address OB82_MDL_ADDR* in the INDEX parameter Enter the ID W#16#00B3 in the SZL_ID parameter (= diagnostic data of a module) CPU 41x OB82 is called For the diagnosis of the relevant components: Call SFB 54 (in the DPV1 environment) MODE= set 1 Diagnostic data are entered in the TINFO and AINFO parameters. Figure 1-9 Diagnostics with CPU 41x Structure of a CPU 41x 1-44 Automation System S7-400 CPU Specifications A5E00165965-01 Diagnostic Addresses in Connection with DP Slave Functionality You assign diagnostic addresses for the PROFIBUS DP in the CPU 41x. Ensure during configuration that DP diagnostic addresses are assigned once to the DP master and once to the DP slave. Specify two diagnostic addresses during configuration: PROFIBUS S7 CPU as DP slaveS7 CPU as DP master Diagnostic address Diagnostic address During the configuration of the DP master, you specify (in the associated project of the DP master) a diagnostic address for the DP slave. In the following, this diagnostic address is described as being assigned to the DP master. During the configuration of the DP slave, you also specify (in the associated project of the DP slave) a diagnostic address that is assigned to the DP slave. In the following, this diagnostic address is described as being assigned to the DP slave. By means of this diagnostic address the DP master receives information on the status of the DP slave or a bus interruption (see also Table 1-9). By means of this diagnostic address the DP slave receives information on the status of the DP master or a bus interruption (see also Table 1-13). Figure 1-10 Diagnostic Addresses for the DP Master and DP Slave Structure of a CPU 41x 1-45 Automation System S7-400 CPU Specifications A5E00165965-01 Event Detection Table 1-9 shows you how the CPU 41x as DP master detects any changes in the operating mode of a CPU as DP slave or interruptions in data transfer. Table 1-9 Event Detection of the CPUs 41x as DP Master Event What Happens in the DP Master Bus interruption (short circuit, connector removed) • OB 86 called with the message Station failure (incoming event; diagnostic address of the DP slave that is assigned to the DP master) • In the case of I/O access: OB 122 called (I/O access error) DP slave: RUN → STOP • OB 82 is called with the message Faulty module (incoming event; diagnostic address of the DP slave that is assigned to the DP master; Variable OB82_MDL_STOP=1) DP slave: STOP → RUN • OB 82 is called with the message Module OK. (outgoing event; diagnostic address of the DP slave that is assigned to the DP master; Variable OB82_MDL_STOP=0) Evaluation in the User Program The following table shows you how, for example, you can evaluate RUN-STOP transitions of the DP slave in the DP master (see also Table 1-9). In the DP Master In the DP Slave (CPU 41x) Diagnostic addresses: (example) Master diagnostic address=1023 Slave diagnostic address in the master system=1022 Diagnostic addresses: (example) Slave diagnostic address=422 Master diagnostic address=not relevant The CPU calls OB 82 with the following information, amongst other things: • OB 82_MDL_ADDR:=1022 • OB82_EV_CLASS:=B#16#39 (incoming event) • OB82_MDL_DEFECT:=module malfunction Tip: This information is also in the diagnostic buffer of the CPU You should also program the SFC 13 “DPNRM_DG” in the user program to read out the DP slave diagnostic data. We recommend you use SFB 54 in the DPV1 environment. It outputs the interrupt information in its entirety. CPU: RUN → STOP CPU generates a DP slave diagnostic frame . Structure of a CPU 41x 1-48 Automation System S7-400 CPU Specifications A5E00165965-01 Address Areas of the Intermediate Memory Configure in STEP 7 the input and output address areas: • You can configure up to 32 input and output address areas. • Each of these address areas can be up to 32 bytes in size • You can configure a maximum of 244 bytes of inputs and 244 bytes of outputs in total An example for the configuration of the address assignments of the intermediate memory is provided in the table below. You will also find this in the online help for STEP 7 configuration. Table 1-10 Configuration Example for the Address Areas of the Intermediate Memory Type Master Address Type Slave Address Length Unit Consistency 1 e 222 A 310 2 Byte Unit 2 A 0 e 13 10 Word Total length : 32 Address areas in the DP master CPU Address areas in the DP slave CPU These parameters of the address areas must be the same for the DP master and DP slave Rules You must adhere to the following rules when working with the intermediate memory: • Assignment of the address areas: – Input data of the DP slave are always output data of the DP master – Output data of the DP slave are always input data of the DP master • You can assign the addresses as you choose. You access the data in the user program with load/transfer commands or with SFCs 14 and 15. You can also specify addresses from the process image input and output table (see also section 1.11.1). Structure of a CPU 41x 1-49 Automation System S7-400 CPU Specifications A5E00165965-01 Note You assign addresses for the intermediate memory from the DP address area of the CPU 41x. You must not reassign the addresses you have already assigned to the intermediate memory to the I/O modules on the CPU 41x. • The lowest address in each address area is the start address of that address area. • The length, unit and consistency of address areas for the DP master and DP slave that belong together must be the same. S5 DP Master If you use an IM 308 C as a DP master and the CPU 41x as a DP slave, the following applies to the exchange of consistent data: You must program FB 192 in the IM 308-C so that consistent data can be transferred between the DP master and DP slave. The data of the CPU 41x are only output or displayed contiguously in a block with FB 192. S5-95 as DP Master If you use an AG S5-95 as a DP master, you must also set its bus parameters for the CPU 41x as DP slave. Structure of a CPU 41x 1-50 Automation System S7-400 CPU Specifications A5E00165965-01 Sample Program The small sample program below illustrates data transfer between the DP master and DP slave. This example contains the addresses from Table 1-10. In the DP Slave CPU In the DP Master CPU L 2 T MB 6 L EB 0 T MB 7 Preprocess data in the DP slave L MW 6 T PQW 310 Transfer data to the DP master L PIB 222 T MB 50 L PIB 223 L B#16#3 + I T MB 51 Continue to process received data in the DP master L 10 + 3 T MB 60 Preprocess data in the DP master CALL SFC 15 LADDR:= W#16#0 RECORD:= P#M60.0 Byte20 RET_VAL:= MW 22 Send data to the DP slave CALL SFC 14 LADDR:=W#16#D RET_VAL:=MW 20 RECORD:=P#M30.0 Byte20 Receive data from the DP master L MB 30 L MB 7 + I T MW 100 Continue to process received data Data Transfer in STOP Mode The DP slave CPU goes into STOP mode: The data in the intermediate memory of the CPU are overwritten with “0”. In other words, the DP master reads “0”. The DP master goes into STOP mode: The current data in the intermediate memory of the CPU are retained and can continue to be read by the CPU. PROFIBUS Address You cannot set 126 as PROFIBUS address for the CPU 41x as DP slave. Structure of a CPU 41x 1-53 Automation System S7-400 CPU Specifications A5E00165965-01 Table 1-12 Reading Out the Diagnostic Data with STEP 5 and STEP 7 in the Master System, Fortsetzung Automation System with DP Master Refer To...ApplicationBlock or Tab in STEP 7 SIMATIC S5 with IM 308-C as DP master FB 192 “IM308C” To read out the slave diagnosis (store in the data area of FBs see the ET 200 Distributed I/O System manual SIMATIC S5 with S5-95U programmable controller as DP master SFB 230 “S_DIAG” the user program) Example of Reading Out the Slave Diagnosis with FB 192 “IM 308C” Here you will find an example of how to use FB 192 to read out the slave diagnosis for a DP slave in the STEP 5 user program. Assumptions The following assumptions apply to this STEP 5 user program: • The IM 308-C is assigned pages 0 to 15 (number 0 of the IM 308-C) as the DP master. • The DP slave has the PROFIBUS address 3. • The slave diagnosis is to be stored in DB 20. However, you can also use any other data block for this. • The slave diagnosis consists of 26 bytes. STEP 5 User Program STL Explanation :A DB 30 :JU FB 192 Name :IM308C DPAD : KH F800 IMST : KY 0, 3 FCT : KC SD GCGR : KM 0 TYP : KY 0, 20 STAD : KF +1 LENG : KF 26 ERR : DW 0 Default address area of the IM 308-C IM no. = 0, PROFIBUS address of DP slave = 3 Function: Read slave diagnosis Not evaluated S5 data area: DB 20 Diagnostic data from data word 1 Length of diagnosis = 26 bytes Error code stored in DW 0 of DB 30 Structure of a CPU 41x 1-54 Automation System S7-400 CPU Specifications A5E00165965-01 Diagnostic Addresses in Connection with DP Master Functionality You assign diagnostic addresses for the PROFIBUS DP in the CPU 41x. Ensure during configuration that DP diagnostic addresses are assigned once to the DP master and once to the DP slave. Specify two diagnostic addresses during configuration: PROFIBUS S7 CPU as DP slaveS7 CPU as DP master Diagnostic address Diagnostic address During the configuration of the DP master, you specify (in the associated project of the DP master) a diagnostic address for the DP slave. In the following, this diagnostic address is described as being assigned to the DP master. During the configuration of the DP slave, you also specify (in the associated project of the DP slave) a diagnostic address that is assigned to the DP slave. In the following, this diagnostic address is described as being assigned to the DP slave. By means of this diagnostic address the DP master receives information on the status of the DP slave or a bus interruption (see also Table 1-9). By means of this diagnostic address the DP slave receives information on the status of the DP master or a bus interruption (see also Table 1-13). Figure 1-12 Diagnostic Addresses for the DP Master and DP Slave Structure of a CPU 41x 1-55 Automation System S7-400 CPU Specifications A5E00165965-01 Event Detection Table 1-13 shows you how the CPU 41x as DP slave detects any operating mode changes or interruptions in data transfer. Table 1-13 Event Detection of the CPUs 41x as DP Slave Event What Happens in the DP Slave Bus interruption (short circuit, connector removed) • OB 86 is called with the message Station failure (incoming event; diagnostic address of the DP slave that is assigned to the DP slave) • In the case of I/O access: OB 122 called (I/O access error) DP master: RUN → STOP • OB 82 is called with the message Faulty module (incoming event; diagnostic address of the DP slave that is assigned to the DP slave; Variable OB82_MDL_STOP=1) DP master: STOP → RUN • OB 82 is called with the message Module OK. (outgoing event; diagnostic address of the DP slave that is assigned to the DP slave; Variable OB82_MDL_STOP=0) Evaluation in the User Program The following table 1-14 shows you, for example, how you can evaluate RUN-STOP transitions of the DP master in the DP slave (see also Table 1-13). Table 1-14 Evaluation of RUN-STOP Transitions in the DP Master/DP Slave In the DP Master In the DP Slave Diagnostic addresses: (example) Master diagnostic address=1023 Slave diagnostic address in the master system=1022 Diagnostic addresses: (example) Slave diagnostic address=422 Master diagnostic address=not relevant CPU: RUN → STOP The CPU calls OB 82 with the following information, amongst other things: • OB 82_MDL_ADDR:=422 • OB82_EV_CLASS:=B#16#39 (incoming event) • OB82_MDL_DEFECT:=module malfunction Tip: This information is also in the diagnostic buffer of the CPU Structure of a CPU 41x 1-58 Automation System S7-400 CPU Specifications A5E00165965-01 Table 1-16 Structure of Station Status 2 (Byte 1) Bit Meaning 0 1: The DP slave must be assigned new parameters and reconfigured. 1 1: A diagnostic message has been issued. The DP slave cannot continue until the problem has been corrected (static diagnostic message). 2 1: The bit is always set to “1” if the DP slave with this DP address is present. 3 1: Response monitoring is enabled for this DP slave. 4 0: The bit is always at “0”. 5 0: The bit is always at “0”. 6 0: The bit is always at “0”. 7 1: The DP slave is disabled – that is, it has been removed from cyclic processing. Table 1-17 Structure of Station Status 3 (Byte 2) Bit Meaning 0 to 6 0: The bits are always at “0”. 7 1: • There are more diagnostic messages than the DP slave can store. • The DP master cannot enter all the diagnostic messages sent by the DP slave in its diagnostic buffer. Master PROFIBUS Address The master PROFIBUS address diagnostic byte contains the DP address of the DP master that: • Assigns parameters for the DP slave and • Has read and write access to the DP slave Table 1-18 Structure of the Master PROFIBUS Address (Byte 3) Bit Meaning 0 to 7 DP address of the DP master that configured the DP slave and has read and write access to the DP slave. FFH: DP slave has not been configured by any DP master. Structure of a CPU 41x 1-59 Automation System S7-400 CPU Specifications A5E00165965-01 Manufacturer ID The manufacturer ID contains a code that describes the type of the DP slave. Table 1-19 Structure of the Manufacturer ID (Bytes 4, 5) Byte 4 Byte 5 Manufacturer ID for CPU 80H C5H 412-1 80H C6H 412-2 80H C7H 414-2 80H C8H 414-3 80H CAH 416-2 80H CBH 416-3 80H CCH 417-4 Structure of a CPU 41x 1-60 Automation System S7-400 CPU Specifications A5E00165965-01 Module Diagnosis The module diagnosis tells you for which of the configured address areas of the intermediate memory an entry has been made. Byte 6 7 0 Bit no. Length of the module diagnosis including byte 6 (depends on the number of configured address areas up to 6 bytes) Byte 7 Set actual configuration and slave CPU in STOP Entry for 2nd configured address area Entry for 3rd configured address area Entry for 4th configured address area Entry for 5th configured address area Bit 8 Entry for 6th to 13th configured address area Code for module diagnosis 0 1 7 6 5 4 1 02 1 3 Entry for 1st configured address area Bit no. Bit no.7 6 5 4 3 Byte 11 Entry 30th configured address area Entry for the 31st configured address area 02 1 Bit no.7 6 5 4 3 Byte 9 Entry for 14th to 21st configured address area 02 1 Bit no.7 6 5 4 3 Bit 10 Entry for 22nd to 29th configured address area 02 1 Bit no.7 6 5 4 3 Entry for the 32nd configured address area 00 00 0 Set actual configuration Set actual configuration Figure 1-14 Structure of the Module Diagnosis of the CPU 41x Structure of a CPU 41x 1-63 Automation System S7-400 CPU Specifications A5E00165965-01 Interrupts with the S7/M7 DP Master In the CPU 41x as a DP slave you can trigger a process interrupt in the DP master from the user program. You can trigger an OB 40 in the user program of the DP master by calling SFC 7 “DP_PRAL”. Using SFC 7 you can forward interrupt information in a double word to the DP master, which you can evaluate in OB 40 in the OB40_POINT_ADDR variable. You can program the interrupt information as you choose. You will find a detailed description of SFC 7 “DP_PRAL” in the System Software for S7-300/400, System and Standard Functions Reference Manual. Interrupts with another DP Master If you are running the CPU 41x with another DP master, these interrupts are reflected in the station diagnosis of the CPU 41x. You have to process the relevant diagnostic events in the DP master’s user program. Note Note the following in order to be able to evaluate diagnostic interrupts and process interrupts by means of the station diagnosis when using a different DP master: • The DP master should be able to store the diagnostic messages; in other words, the diagnostic messages should be stored in a ring buffer in the DP master. There are more diagnostic messages than the DP master can store, only the last diagnostic message received would be available for evaluation, for example. • You must query the relevant bits in the station diagnosis at regular intervals in your user program. You must also take the PROFIBUS DP bus cycle time into consideration so that you can query the bits at least once synchronously with the bus cycle time, for example. • You cannot use process interrupts in the station diagnosis with an IM 308-C as the DP master, because only incoming – and not outgoing – interrupts are reported. Structure of a CPU 41x 1-64 Automation System S7-400 CPU Specifications A5E00165965-01 1.12 Direct Communication You can configure direct communication for PROFIBUS nodes as of STEP 7 V 5.x. The CPU 41x can participate in direct communication as the sender or recipient. “Direct Communication” represents a special type of communication relationship between PROFIBUS DP nodes. 1.12.1 Principle of Direct Data Direct communication is characterized by the fact that PROFIBUS DP nodes “listen in” to find out which data a DP slave is sending back to its DP master. By means of this mechanism the “eavesdropper” (recipient) can access changes to the input data of remote DP slaves directly. During configuration in STEP 7, you specify by means of the relevant I/O input addresses the address area of the recipient to which the required data of the sender are to be read. A CPU 41x can be: Sender as a DP slave Recipient as a DP slave or a DP master or as a CPU that is not integrated in a master system (see Figure 1-17). Structure of a CPU 41x 1-65 Automation System S7-400 CPU Specifications A5E00165965-01 Example Figure 1-17 uses an example to illustrate which direct communication “relationships” you can configure. All the DP masters and DP slaves in the figure are CPUs 41x. Note that other DP slaves (ET 200M, ET 200X, ET 200S) can only be senders. PROFIBUS CPU 41x as DP master 1 CPU 41x-2 DP slave 3 DP slave 5 CPU 41x as DP slave 1 DP master system 1 DP master system 2 CPU 41x as DP master 2 CPU 41x as DP slave 2 CPU 41x as DP slave 4 Figure 1-17 Direct Communication with CPUs 41x Structure of a CPU 41x 1-68 Automation System S7-400 CPU Specifications A5E00165965-01 1.13 Consistent Data Data that belongs together in terms of its content and a process state written at a specific point in time is known as consistent data. To maintain consistency, the data should not be changed or updated during processing or transmission. Example To ensure that the CPU has a consistent image of the process signals for the duration of cyclic program scanning, the process signals are read from the process image inputs prior to program scanning and written to the process image outputs after the program scanning. Subsequently, during program scanning when the address area “inputs” (I) and “outputs” (O) are addressed, the user program addresses the internal memory area of the CPU on which the image of the inputs and outputs is located instead of directly accessing the signal modules. SFC 81 “UBLKMOV” With SFC 81 “UBLKMOV” (uninterruptible block move), you can copy the contents of a memory area (= source area) consistently to a different memory area (= destination area). The copy operation cannot be interrupted by other operating system activities. SFC 81 “UBLKMOV” enables you to copy the following memory areas: • Memory markers • DB contents • Process image of the inputs • Process image of outputs The maximum amount of data you can copy is 512 bytes. Take into consideration the restrictions for the specific CPU, which are documented in the operations list, for example. Since copying cannot be interrupted, the interrupt reaction times of your CPU may increase when using SFC 81 “UBLKMOV”. The source and destination areas must not overlap. If the specified destination area is larger than the source area, the function only copies as much data to the destination area as that contained in the source area. If the specified destination area is smaller than the source area, the function only copies as much data as can be written to the destination area. Structure of a CPU 41x 1-69 Automation System S7-400 CPU Specifications A5E00165965-01 1.13.1 Consistency for Communication Blocks and Functions Using S7-400 the communication data is not processed in the scan cycle checkpoint; instead, this data is processed in fixed time slices during the program cycle. In the system the byte, word and double word data formats can always be processed consistently, in other words, the transfer or processing of 1 byte, 1 word (= 2 bytes) or 1 double word (= 4 bytes) cannot be interrupted. If communication blocks (such as SFB 12 “BSEND”) are called in the user program, which are only used in pairs (such as SFB 12 “BSEND” und SFB 13 “BRCV”) and which share access to data, the access to this data area can be coordinated between themselves, using the “DONE” parameter, for example. Data consistency of the communication areas transmitted locally with a communication block can thus be ensured in the user program. S7 communication functions such as SFB 14 “GET”, SFB 15 “PUT” react differently because no block is needed in the user program of the destination device. In this case the size of data consistency has to be taken into account beforehand during the programming phase. 1.13.2 Access to the Working Memory of the CPU The communication functions of the operating system access the working memory of the CPU in fixed block lengths. The block size is a variable length up to a maximum of 462 bytes. 1.13.3 Read from and Writing to a DP Standard Slave Consistently Writing Data Consistently to a DP Standard Slave Using SFC 14 “DPRD_DAT” Using SFC 14 “DPRD_DAT” (read consistent data of a DP standard slave) you can consistently read the data of a DP standard slave. The data read is entered into the destination range defined by RECORD if no error occurs during the data transmission. The destination range must have the same length as the one you have configured for the selected module with STEP 7. By invoking SFC 14 you can only access the data of one module / DP ID at the configured start address. Structure of a CPU 41x 1-70 Automation System S7-400 CPU Specifications A5E00165965-01 1.13.4 Writing Data Consistently to a DP Standard Slave Using SFC 15 “DPWR_DAT” Using SFC 15 “DPWR_DAT” (write consistent data to a DP standard slave) you can consistently write data to the DP standard slave addressed in the RECORD. The source range must have the same length as the one you have configured for the selected module with STEP 7. Note The Profibus DP standard defines the upper limit for the transmission of consistent user data (see following section). Typical DP standard slaves adhere to this upper limit. In older CPUs (<1999) there are restrictions in the transmission of consistent user data depending on the CPU. For these CPUs you can determine the maximum length of the data which the CPU can consistently read and write to and from the DP standard in the respective technical specifications under the index entry “DP Master – User data per DP slave”. Newer CPUs are capable of exceeding the value for the amount of data that a DP standard slave can send and receive. Upper Limit for the Transmission of Consistent User Data on a DP Slave The Profibus DP standard defines the upper limit for the transmission of consistent user data to a DP slave. For this reason a maximum of 64 words = 128 bytes of user data can be consistently transferred in a block to the DP slave. During the configuration you can determine the size of the consistent area. You can set a maximum length of consistent data at 64 words = 128 bytes in the special identification format (SKF) (128 bytes for inputs and 128 bytes for outputs); the data block size cannot exceed this. This upper limit only applies to pure user data. Diagnostics and parameter data are regrouped into full records and therefore always transferred consistently. In the general identification format (AKF) the maximum length of consistent data can be set at 16 words = 32 bytes (32 bytes for inputs and 32 bytes for outputs); the data block size cannot exceed this. Note in this context that a CPU 41x in a general environment acting as a DP slave on a third-party master (connection defined by GSD) has to be configured with the general identification format. The transfer memory of a CPU 41x acting as a DP slave to the PROFIBUS DP can therefore be a maximum of 16 words = 32 bytes. 2-1 Automation System S7-400 CPU Specifications A5E00165965-01 Memory Concept and Startup Scenarios Chapter Overview In Section Description On Page 2.1 Overview of the Memory Concept of S7-400 CPUs 2-2 2.2 Overview of the Startup Scenarios for S7-400-CPUs 2-5 2 Memory Concept and Startup Scenarios 2-2 Automation System S7-400 CPU Specifications A5E00165965-01 2.1 Overview of the Memory Concept of S7-400 CPUs Subdivision of the Memory Areas You can divide the memory of the S7 CPUs into the following areas: Integrated load memory RAM with battery backup External load memory RAM with battery backup or retentive flash memory Working memory code For the program RAM with battery backup Process input and output image Diagnostic buffer Working memory data For data RAM with battery backup Local data stack Load memory For project data (blocks, symbols, comments, configu- ration and parameter assignment data) Working memory For runtime-relevant blocks System memory Contains memory marker, timers, counters, block stack and interrupt stack RAM with battery backup Memory Concept and Startup Scenarios 2-3 Automation System S7-400 CPU Specifications A5E00165965-01 Important Note for CPUs with Configurable Division of the Working Memory If you use parameter assignment to change the division of the working memory, the working memory is reorganized when the system data are downloaded to the CPU. The result of this is that data blocks that were created with SFC are deleted, and the remaining data blocks are assigned initial values from the load memory. The usable size of the working memory for code or data blocks is changed if you change the following parameters for loading the system data: • Size of the process image (byte by byte; “Cycle/Clock Memory” tab) • Communication resources (S7-400 only; “Memory” tab) • Size of the diagnostic buffer (“Diagnostics/Clock” tab) • Number of local data for all priority classes (“Memory” tab) Basis for Calculating the Required Working Memory To ensure that you do not exceed the available amount of working memory in the CPU, you must take into consideration the following memory requirements when assigning parameters: Table 2-1 Memory Requirements Parameter Required Working Memory In Code/Data Memory Size of the process image (inputs) 12 bytes per byte in the process input image Code memory Size of the process image (outputs) 12 bytes per byte in the process output image Code memory Communication resources (communication jobs) 72 bytes per communication job Code memory Size of diagnostic buffer 20 bytes per entry in the diagnostic buffer Code memory Volume of local data 1 byte per byte of local data Data memory Memory Concept and Startup Scenarios 2-6 Automation System S7-400 CPU Specifications A5E00165965-01 3-1 Automation System S7-400 CPU Specifications A5E00165965-01 Cycle and Reaction Times of the S7-400 This chapter explains the composition of the cycle and reaction times of the S7-400. You can display the cycle time of your user program on the relevant CPU using the programming device (see manual Configuring Hardware and Communication Connections with STEP 7 Version 5.0 or higher). Examples will illustrate how you calculate the cycle time. The reaction time is important for monitoring a process. This chapter provides a detailed description of how to calculate this. If you use a CPU 41x-2 DP as a master in the PROFIBUS DP network, you also have to take into account DP cycle times (see Section 3.5). Chapter Overview Section Description Page 3.1 Cycle time 3-2 3.2 Cycle Time Calculation 3-4 3.3 Different Cycle Times 3-8 3.4 Communication Load 3-10 3.5 Reaction Time 3-13 3.6 How Cycle and Reaction Times Are Calculated 3-18 3.6 Examples of Calculating the Cycle Time and Reaction Time 3-18 3.8 Interrupt Reaction Time 3-22 3.9 Example of Calculating the Interrupt Reaction Time 3-24 3.10 Reproducibility of Time-Delay and Watchdog Interrupts 3-25 Further Information You will find further information on the following processing times in the S7-400 Instruction List. It lists all the STEP 7 instructions that can be processed by the relevant CPUs, together with their execution times and all the SFCs/SFBs integrated in the CPUs and the IEC functions that can be called in STEP 7, together with their processing times. 3 Cycle and Reaction Times of the S7-400 3-2 Automation System S7-400 CPU Specifications A5E00165965-01 3.1 Cycle Time In this chapter you will learn about the composition of the cycle time and how you can calculate the cycle time. Definition of the Cycle Time The cycle time is the time which the operating system needs to process a program run – in other words, an OB 1 run – and all the program segments and system activities that interrupt that run. This time is monitored. Time-Sharing Model Cyclic program scanning, and thus also processing of the user program, is performed in time slices. So that you can better appreciate these processes, we will assume in the following that each time slice is exactly 1 ms long. Process Image The process signals are read or written prior to program scanning so that a consistent image of the process signals is available to the CPU for the duration of cyclic program scanning. Then the CPU does not directly access the signal modules during program scanning when the address area “inputs” (I) and “outputs” (O) are addressed, but addresses instead the internal memory area of the CPU on which the image of the inputs and outputs is located. Cycle and Reaction Times of the S7-400 3-5 Automation System S7-400 CPU Specifications A5E00165965-01 Process Image Updating The table below shows the CPU times for process image updating (process image transfer time). The times listed in the table are “ideal values” that may be increased by the occurrence of interrupts and by CPU communications. The transfer time for process image updating is calculated as follows C + portion in central rack (from line A of the following table) + portion in expansion rack with local connection (from line B) + portion in expansion rack with remote connection (from line C) + portion via integrated DP interface (from line D) + portion of consistent data via integrated DP interface (from line E1) + portion of consistent data via external DP interface (from line E2) = transfer time for process image updating The following tables list the individual portions of the transfer times for updating the process image (process image transfer time), once for standard CPUs and once for redundant CPUs. The times listed in the table are “ideal values” that may be increased by the occurrence of interrupts and by CPU communications. Table 3-3 Portions of the process image transfer time Portions n = number of bytes in the process image c= number of consistency areas ****) in the process image CPU 412 CPU 414 CPU 417 CPU 416 C Base load 30 s 20 s 18 s A In the central rack *) **) n * 1.9 s n * 1.9 s n * 1.9 s B In the expansion rack with local connection **) n * 5 s n * 5 s n * 5 s C In the expansion rack with remote connection **) ***) n * 10 s n * 10 s n * 10 s D In the DP area for the integrated DP interface n * 0.5 s n * 0.5 s n * 0.5 s E 1 Consistent data in the process image for the integrated DP interface k * 40 s + n * 0.5 s k * 27 s + n * 0.5 s k * 22 s + n * 0.5 s E 2 Consistent data in the process image for the external DP interface (CP 443-5 extended) k * 40 s + n * 3.2 s k * 27 s + n * 3.2 s k * 22 s + n * 2.1 s *) Also applies to the external DP interface (CP 443-5 extended) **) In the case of I/O modules that are plugged into the central rack or an expansion rack, the specified value contains the runtime of the I/O module ***) Measured with the IM 460-3 and IM 461-3 with a connection length of 100 m ****) The areas set in HW Config that are written to or read from the I/O at once and are therefore consistent. Cycle and Reaction Times of the S7-400 3-6 Automation System S7-400 CPU Specifications A5E00165965-01 Table 3-4 Portions of the process image transfer time, H CPUs Portions n = number of bytes in the process image m= number of accesses to the process image *) c= number of consistency areas in the process image CPU 41x-4H single mode CPU 41x-4H redundant C Base load 20 s 20 s A **) In the central rack Read byte/word/double word Write byte/word/double word (m * 23 + n * 1.9) s (m * 17 + n * 1.9) s (m * 28 + n* 1.9) s (m * 20 + n * 1.9) s B **) In the expansion rack with local connection Read byte/word/double word Write byte/word/double word (m * 23 + n * 5) s (m * 17 + n * 5) s (m * 28 + n * 5) s (m * 20 + n * 5) s C **) ***) In the expansion rack with remote connectionRead byte/word/double word Write byte/word/double word (m * 23 + n * 10) s (m * 17 + n * 10) s (m * 28 + n * 10) s (m * 20 + n * 10) s D In the DP area of the integrated DP interfaceRead byte/word/double word Write byte/word/double word (m * 23 + n * 0.5) s (m * 17 + n * 0.5) s (m * 28 + n * 0.5) s (m * 20 + n * 0.5 s E1 Consistent data in the process image for the integrated DP interface Reade data Write data (k * 50 + n * 0.6) s (k * 50 + n * 0.6) s (k * 100 + n * 1.2)s (k * 100 + n * 0.6)s E2 Consistent data in the process image for the external DP interface (CP 443-5 extended) Read data Write data (k * 50 + n * 3.4) s (k * 50 + n * 3.4) s (k * 100 + n * 4.0)s (k * 100 + n * 3.4)s *) The data of a module are updated with the minimal number of accesses. (E.g.: For 8 bytes there are two double word accesses, for 16 bytes four 4 double word accesses.) **) In the case of I/O modules that are plugged into the central rack or an expansion rack the specified value contains the runtime of the I/O module. ***) Measured with the IM 460-3 and IM 461-3 with a connection length of 100 m Cycle and Reaction Times of the S7-400 3-7 Automation System S7-400 CPU Specifications A5E00165965-01 Increasing the Cycle Time of the CPU 41x-4H With the CPU 41x-4H, you must further multiply the calculated cycle time by a factor specific to the CPU in question. This factor is shown in the table below: Table 3-5 User program processing time for the CPU 41x-4H Process CPU 41x-4H single mode CPU 41x-4H redundant Factor 1.03 1.14 Operating System Scan Time at the Scan Cycle Checkpoint The table below lists the operating system scan times at the scan cycle checkpoint of the CPUs. Table 3-6 Operating system scan time at scan cycle checkpoint Process CPU 412-1 412-2 CPU 414-2 414-3 CPU 416-2 416-3 CPU 417-4 CPU 41x-4H single mode CPU 41x-4H redundant Scan cycle control at the SCC 240 s 170 s 135 s 170 s 190 -1770 s ∅ 200 s 395 - 1865 s ∅ 445 s Increase in Cycle Time by Nesting Interrupts Table 3-7 Increase in Cycle Time by Nesting Interrupts CPU Hardware Interrupt Diagnostic Interrupt Day Interrupt Time-Delay Interrupt Watchdog Interrupt Programming/ Periphery Access Error CPU 412-1/-2 520 s 590 s 490 s 370 s 370 s 180 s / 190 s CPU 414-2/-3 370 s 420 s 350 s 260 s 260 s 130 s / 140 s CPU 416-2/-3 300 s 340 s 280 s 210 s 210 s 100 s / 105 s CPU 417-4 370 s 420 s 350 s 260 s 260 s 130 s / 140 s CPU 41x-4 H single mode 390 s 450 s 310 s 270 s 255 s 140 s / 170 s CPU 41x-4 H redundant 705 s 785 s 560 s 530 s 530 s 175 s / 240 s You have to add the program execution time at the interrupt level to this increase. If several interrupts are nested, their times must be added together.