High-performance Ge-on-Si photodetectors

High-performance Ge-on-Si photodetectors

(Parte 1 de 4)

NATURE PHOTONICS | VOL 4 | AUGUST 2010 | w.nature.com/naturephotonics 527

For many years, high-quality Germanium (Ge) crystals have been used as the primary material for highly sensitive near-infrared detectors. Such detectors are usually cooled to around 7 K to reduce dark currents, making them expensive and of limited use, particularly for spectroscopy. However, within the past ten years, the use of Ge in detector applications has changed dramatically. Th is development was triggered by the ability to grow Ge epitaxially on silicon (Si). Rather than using single-crystal bulk Ge, the use of Si as a substrate not only reduced device cost but also enabled completely new applications for Ge in optical communications, which until then had typically been covered by compound semiconductors such as InGaAs.

Th e epitaxial growth of Ge on Si is diffi cult because of the 4.2% lattice mismatch between the two elements. In the 1990s, the fi rst attempts were made to epitaxially grow Ge on Si at reasonably low dislocation densities, primarily motivated by the higher mobilities for electrons and holes in Ge than in Si. Th is Review fi rst describes the techniques that eventually yielded high-quality Ge-on-Si devices. Initially this progress was used to develop free-space Ge detectors with responsivities and speeds comparable to group i–v semiconductor detectors. Th e development of the free-space Ge detector, and the following evolution to the waveguide-integrated Ge detector, is discussed. Th is evolution not only enabled electronic–photonic integration on silicon but also achieved higher performance by eliminating the trade-off between bandwidth and quantum effi ciency. Diff erent coupling schemes and their corresponding performances are also reviewed. Finally, the recent progress of Ge-based avalanche photodetectors is discussed, as these important devices are currently competing with group i–v avalanche photodetectors for a market share in optical communications.

Choice of materials Growth of high-quality Ge epitaxial fi lms on Si. Th e greatest challenge for high-quality Ge epitaxy on Si is the 4.2% lattice mismatch between the two materials. Th is mismatch causes two serious issues: high surface roughness resulting from the Stransky–Krastanov growth, and a high density of threading dislocations in the Ge epitaxial layer. High surface roughness hinders the process of integrating Ge devices with Si electronics because complementary metal–oxide–semiconductor (CMOS) devices require planar processing, whereas a high density of threading dislocations severely aff ects the performance of Ge devices because of the recombination centres that are introduced along these dislocations.

High-performance Ge-on-Si photodetectors

Jurgen Michel*, Jifeng Liu and Lionel C. Kimerling

The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

Th e fi rst successful approach for growing high-quality epitaxial Ge layers on Si was reported in a forward-looking paper by Luryi et al. in 19841. In this study, a graded SiGe buff er layer, grown in a molecular beam epitaxy chamber, was used to reduce the threading dislocation density in the Ge layer. Th is method was later improved by Fitzgerald et al. using optimized SiGe graded buff er layers2–5. A low grading rate of ~10% Ge per micrometre was adopted to minimize dislocation nucleation rates. Choosing adequate growth temperatures for diff erent SiGe compositions gave a high dislocation glide velocity but slow dislocation nucleation kinetics, allowing the fi lm to relax mainly by gliding existing threading dislocations instead of generating additional dislocations. At 50% Ge composition, an ex situ chemical mechanical polishing step was used to remove crosshatch surface roughness and greatly reduce the dislocation pile-up formation that hinders dislocation gliding. For SiGe growth with Ge content of more than 50%, the growth

MIT Microphotonics Center, Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA. *e-mail: jmichel@mit.edu

Ge Si a b

Figure 1 | Transmission electron microscope cross-sections of Ge-on-Si layers for Ge epitaxial growth at diff erent temperatures. a, Stransky– Krastanov growth of Ge-on-Si at 550 °C in an ultrahigh vacuum CVD reactor. b, Ge-on-Si grown at 335 °C in an ultrahigh vacuum CVD reactor. The thickness of the Ge layer shown here is 60 nm.

528 NATURE PHOTONICS | VOL 4 | AUGUST 2010 | w.nature.com/naturephotonics temperature was gradually decreased to accommodate the reduction in the yield strength of the material and to prevent nucleation of dislocations. Th is approach was used to successfully demonstrate Ge fi lms with threading dislocations of <2 × 106 cm–2.

High-quality epitaxial Ge-on-Si growth has also been achieved through adequate direct Ge growth without using SiGe buff ers layers. In this case, a two-step Ge growth technique is used to prevent islanding during the ultrahigh vacuum chemical vapour deposition (CVD) process, with subsequent annealing to signifi cantly decrease the threading dislocation density6–8. In the initial growth step, a thin epitaxial Ge buff er layer of 30–60 nm is directly grown on Si at 320–360 ºC. At such low growth temperatures, the low surface diffusivity of Ge kinetically suppresses the islanding of Ge. Th e growth temperature in the main growth step is increased to >600 ºC to achieve higher growth rates and better crystal quality. If the low-temperature buff er layer is thick enough (>30 nm), the Ge atoms are no longer infl uenced by the Ge/Si lattice mismatch and so homoepitaxial Ge growth results. Th e fi lm therefore remains fl at even at elevated growth temperatures, and fully planar growth is achieved. Figure 1 shows cross-sectional transmission electron microscope images of Ge-on-Si grown by the single- (Fig. 1a) and two-step (Fig. 1b) growth methods. Th e threading dislocation density of the as-grown (that is, without post-growth annealing) fi lm is typically of the order of 108–109 cm–2. Adequate post-growth annealing at >750 ºC can reduce the threading dislocation density by up to two orders of magnitude8. Koester et al. have extended this two-step approach by demonstrating growth of Ge on an ultrathin silicon-on-insulator surface9,10. In this case, however, the thermal annealing process for reducing threading dislocations is compromised by interdiff usion between Si and Ge layers, which is possibly related to the instability of the ultrathin silicon-on-insulator layer.

Another direct Ge growth approach uses H2 annealing at around 825 ºC instead of a two-step growth process to reduce the surface roughness and threading dislocation density of epitaxial Ge fi lms11,12.

Th e enhanced atomic mobility under H2 annealing was proposed to be the major mechanism for the reduction in surface roughness and defect density.

Diff erent approaches have been developed in recent years to achieve high-quality Ge epitaxy on Si at lower temperatures. For example, the thin Ge buff er layer was altered by combining thin SiGe buff er layers (<<1 μm) with the two-step Ge growth approach13,14. A low threading dislocation density of <7 × 106 cm–2 was reported. Very recently, low-energy plasma-enhanced CVD has been developed to achieve high-quality Ge at a lower thermal budget than ultrahigh vacuum or low-pressure CVD15.

Tensile-strained Ge-on-Si. Strain has a signifi cant eff ect on the band structure and optoelectronic properties of semiconductor epitaxial layers. It is therefore important to understand and engineer the strain in epitaxial fi lms for optoelectronic applications. Th e eff ect of tensile strain on the band structure of Ge at 300 K is shown in Fig. 2. Relaxed Ge has an indirect gap of 0.664 V at the L valley (in <1> directions), and a direct gap of 0.800 eV at the Γ valley (k = 0). When biaxial tensile stress is applied, both the direct and indirect gaps shrink, but the direct gap shrinks faster. Th erefore, Ge transforms from an indirect to a direct gap material with the increase of tensile strain, and its optoelectronic properties are greatly enhanced accordingly. Compressive strain, on the other hand, increases the diff erence between the direct and indirect gaps of Ge, which is detrimental to its optoelectronic properties. It is therefore desirable to have tensile-strained Ge instead of compressive-strained Ge for high-performance optoelectronic devices on Si.

Because the lattice constant of Ge is greater than that of Si, very thin epitaxial Ge layers (tens of nanometres) and Ge nanostructures on Si are usually compressively strained. However, because the critical thickness for two-dimensional coherent growth of Ge on Si without relaxation is usually only around three monolayers (~0.814 nm) because of the signifi cant lattice mismatch16,17, a Ge layer thicker than 200 nm can nearly completely relax at growth temperatures above 600 ºC. When cooled to room temperature, tensile strain — instead of compressive strain — can accumulate in the Ge layers because of the larger thermal expansion coeffi cient of Ge compared with Si. Th is is usually the case for epitaxial Ge fi lms fabricated by the two-step growth for optoelectronic applications, as the Ge fi lm thickness required for a strong interaction with nearinfrared light is usually >200 nm, and the second step of growth is usually performed at temperatures above 600 ºC (refs 18–20). A thermally induced tensile strain of 0.25% has been achieved using this approach. In recent years, relaxed GeSn buff er layers on Si have been developed as a lattice template for tensile strained Ge (refs 21,2) to further enhance the tensile strain in Ge. Th is approach has so far achieved tensile strains of up to 0.68% (ref. 23).

Selective growth of Ge on Si. For the integration of Ge-on-Si devices into Si-based circuits, it is highly desirable to grow Ge selectively within designated regions on the Si substrate. Selected Ge growth will aid the process fl ow and allow transistors to be fabricated before the Ge processing stage. Furthermore, selective growth reduces the threading dislocation density if the selective growth region is small enough (<40 μm), as dislocations can glide to the edge of the mesas and annihilate8,24. In recent years, selective growth has also been applied to epitaxial necking and lateral overgrowth for achieving high-quality Ge-on-Si growth25,26. Th e selective growth of SiGe and Si with gas precursors has been developed since the mid-1980s27. Selective growths are usually achieved by using a dielectric mask layer such as SiO2 or Si3N4. Openings are etched through the dielectric layer and reach the surface of the single-crystal Si layer; Ge can be selectively grown in these windows at adequate growth rates. An

SiO2 mask is used because the reaction between the SiO2 mask layer and GeH4 and/or Ge atoms is thought to be what forms volatile GeO

Conduction band

Light hole band Heavy hole band

Biaxial tensile stress L

Tensile strain (%)

Ener gy ( eV)

Eg (L)

Eg () L a b

Figure 2 | The eff ect of tensile strain on the band structure of Ge. a, Schematic of how the band diagram changes as biaxial tensile strain is applied. b, Plot of the bandgap energies for the Γ (E(Γ)) and L (E(L)) bands as a function of tensile strain.

NATURE PHOTONICS | VOL 4 | AUGUST 2010 | w.nature.com/naturephotonics 529 under high vacuum and prevents the nucleation of poly-Ge on SiO2 (refs 28,29). To maintain the selective growth, Ge must be deposited at a slower rate than the desorption rate of Ge-related volatile species; otherwise Ge islands begin to nucleate on the dielectric layer and so the selectivity is lost.

Figure 3a shows a three-dimensional atomic force microscope image of a selectively grown Ge mesa. Th e mesa is faceted, with the (1) and (113) facets dominating when the oxide openings are aligned to a <011> direction. Similar orientation-dependent faceting is also observed in the case of a selective Si homoepitaxy.

Th e selective growth of Ge provides new methods of defi ning Ge photonic structures on Si. By completely fi lling the oxide windows and suppressing faceting, Ge growth can be included in a planar CMOS process fl ow, as shown in Fig. 3b.

Normal-incidence photodetectors Th e fi rst platform for high-performance Ge-on-Si photodetectors was normal-incidence detectors for free-space or fi bre-optic coupling. Th is section reviews the advances and shortcomings of normal-incidence detectors, including the design parameters for high-speed detectors, the graded-index buff er approach, Ge-on-insulator detectors and Ge-on-Si detectors.

Historically, although Ge did have the distinct advantage of ease of integration with Si over InGaAs for light detection in the telecommunications wavelength range of 1,300–1,600 nm, performance of these Ge detectors needed to be as good as or better than the competing group i–v detectors. High responsivities, high bandwidths and low dark currents were therefore mandatory.

Th ermionic emission limits the dark current density in Ge photodiodes to ~10–2 mA cm–2 at room temperature, which is around two orders of magnitude higher than competing InGaAs semiconductor photodetectors. A dark current density of 0.15 mA cm –2 at a reverse bias of −1 V is among the lowest reported for Ge-on-Si devices4, and this is due to the low dislocation densities for Ge photodiodes fabricated on optimized SiGe graded buff er layers. Despite the high Ge quality and low dark currents present in this study, the thin depletion region of 0.3 μm resulted in low responsivity. In view of the integration with Si CMOS circuits, the thick SiGe buff er layer (~10 μm) required to achieve high-quality Ge makes integration diffi cult.

For a long time it was thought that a high-quality Ge detector would require near-perfect crystal quality. It was also suspected that dislocations — threading dislocations in particular — would increase dark current and therefore degrade device quality. Using thin Ge30–39 or SiGe13,40,41 buff er layers therefore seemed counterintuitive for achieving high-performance devices, as their threading dislocation densities are ~10 times higher than in optimized SiGe graded buff er layers. However, Ge photodetectors based on thin buff ers and p-i-n (p-type/intrinsic/n-type layers) structures were found to exhibit a signifi cant built-in electric fi eld of several kV cm–1 inside the intrinsic Ge layer, making the carrier collection dependent not on carrier diff usion but rather on carrier drift 20,3. Th is diff erence is signifi cant because a dependency on carrier diffusion results in a relatively long transit time and signifi cant carrier recombination at dislocations or point defects, thereby reducing the collection effi ciency of the detector. Carrier drift , on the other hand, ignores recombination centres that have recombination times larger than the time it takes for a carrier to drift to the electrodes. For thin Ge layers of the order of 1–2 μm, a strong enough built-in electric fi eld for carrier collection can easily overcome recombination processes at lattice defects. Th e built-in electric fi eld was therefore the enabler for thin, high-quality Ge-on-Si photodetectors. Th e fi rst Ge photodetectors with a thin buff er and reduced threading dislocation density through post-growth annealing showed remarkable responsivities over a large wavelength range30, with an internal quantum effi ciency of 95% at 1,300 nm for a bias of −1 V. To mask the highly dislocated buff er layer, the detectors were designed as vertical junction devices, with one terminal being the p+ Si substrate. During the post-growth thermal treatment, boron from the Si substrate diff uses into the highly dislocated Ge buff er layer, making it form part of the bottom terminal. Using an improved device design with vertical n+-Si/i-Ge/p+-Si heterojunctions to further enhance the built-in fi eld, an internal quantum effi ciency of above 90% in the wavelength range of 650–1,340 nm was achieved at zero bias voltage33. At longer wavelengths of 1,500 nm and above, the internal quantum effi ciency decreases signifi cantly owing to the smaller absorption coeffi cient and the limited absorption length defi ned by the fi lm thickness in the normal-incidence confi guration. Th e internal quantum effi ciency can, however, be enhanced by using a resonant cavity. For example, a resonant cavity Ge detector designed for response at 1,538 nm has been used to improve the internal quantum effi ciency to 59%32.

(Parte 1 de 4)