Baixe sadiku 5ª edição circuitos eletricos e extras - chapt08pp 120121 e outras Notas de estudo em PDF para Engenharia Elétrica, somente na Docsity! Sunday, June 26, 2011 CHAPTER 8 P.P.8.1 (a) At t = 0–, we have the equivalent circuit shown in Figure (a). vL 10  i(0–) = 24/(2 + 10) = 2 A, v(0–) = 2i(0–) = 4 V hence, v(0+) = v(0–) = 4 V. (b) At t = 0+, the switch is closed. L(di/dt) = vL, leads to (di/dt) = vL/L But, vC(0 +) + vL(0 +) = 24 = 4 + vL(0+), or vL(0+) = 20 V (di(0+)/dt) = 20/0.4 = 50 A/s C(dv/dt) = iC leading to (dv/dt) = iC/C But at node a, KCL gives i(0+) = iC(0 +) + v(0+)/2 = 2 = iC(0 +) + 4/2 or iC(0 +) = 0, hence (dv(0+)/dt) = 0 V/s (c) As t approaches infinity, the capacitor is replaced by an open circuit and the inductor is replaced by a short circuit. v() = 24 V, and i() = 12 A. 50mF 2  (a) + v  24V +  2  (b) + vC  24V +  +a i i P.P.8.2 (a) At t = 0-, we have the equivalent circuit shown in (a). 5  5  iL(0-) = –6A, vL(0 –) = 0, vR(0 –) = 0 At t = 0+, we have the equivalent circuit in Figure (b). At node b, iR(0 +) = iL(0 +) + 6, since iL(0 +) = iL(0 –) = –6A, iR(0 +) = 0, and vR(0+) = 5iR(0+) = 0. Thus, iL(0) = –6 A, vC(0) = 0, and vR(0 +) = 0. (b) dvC(0 +)/dt = iC(0 +)/C = 4/0.2 = 20 V/s. To get (dvR/dt), we apply KCL to node b, iR = iL + 6, thus diR/dt = diL/dt. Since vR = 5iR, dvR/dt = 5diR/dt = 5diL/dt. But LdiL/dt = vL, diL/dt = vL/L. Hence, dvR(0 +)/dt = 5vL(0 +)/L. Applying KVL to the middle mesh in Figure (b), –vC(0 +) + vR(0 +) + vL(0 +) = 0 = 0 + 0 + vR(0 +), or vR(0 +) = 0 Hence, dvR(0 +)/dt = 0 = diL(0 +)/dt; diL(0 +)/dt = 0, dvC(0 +)/dt = 20 V/s, dvR(0 +)/dt = 0. (a) iL iR 6A 4A + vL  2H 10 F a b +  + vR vC (b) 6A  P.P.8.6 For t < 0, the switch is closed. The inductor acts like a short circuit while the capacitor acts like an open circuit. Hence, i(0) = 3A and v(0) = 0. -3) = 6.25  = 1/(2RC) = 1/(2x20x4x10 3 o 10x4x101LC1  = 5 Since  >  , this is an overdamped response. o 25)25.6(25.6 2o 2  = = –2.5 and –10 s1,2 Thus, v(t) = A1e -2.5t -10t + A e2 v(0) = 0 = A + A , which leads to A = –A1 1 2 2 dv(0)/dt = –(v(0) + Ri(0))/(RC) = –(20x4.5)12.5 = –1125 But, dv/dt = –2.5A1e -2.5t –10A e-10t 2 At t = 0, –1125 = –2.5A – 10A = 7.5A since A = –A2 1 2 1 1 A = –150, A = 150 1 2 Thus, v(t) = 150(e–10t –2.5t – e ) V P.P.8.7 The initial capacitor voltage is obtained when the switch is in position a. v(0) = [2/(2 + 1)]18 = 12 V The initial inductor current is i(0) = 0. When the switch is in position b, we have the RLC circuit with the voltage source.  = R/(2L) = 10/(2x2.5) = 2 )40/1(x)2/5(1LC1o  = 4 Since  <  , we have an underdamped case. o 16)2(2 2o 2  = = -2  j 3.464 s1,2 Thus, v(t) = vf + [(A1cos3.464t + A sin3.464t)e -2t] 2 where vf = v() = 15, the final capacitor voltage. We now impose the initial conditions to get A and A . 1 2 v(0) = 12 = 15 + A leads to A = –3 1 1 The initial capacitor current is the same as the initial inductor current. i(0) = C(dv(0)/dt) = 0 therefore, dv(0)/dt = 0 But, dv/dt = 3.464[{–A1sin(3.464t) + A cos(3.464t)}e -2t] 2 –2t–2[{A cos(3.464t) + A sin(3.464t)}e ] 1 2 dv(0)/dt = 0 – 2A + 3.464A , which leads to A = –6/3.464 = –1.7321 1 2 2 Thus, v(t) = {15 + [(–3cos(3.464t) – 1.7321sin(3.464t)]e-2t} V i = C(dv/dt), v = Ri = RC(dv/dt) = (1/4)dv/dt R –2t = (1/4)[(6 – 6)cos(3.464t) + (2x1.7321 + 3x3.464)sin(3.464t)]e (t) = (3.464sin(3.464t)e–2t) V vR P.P.8.8 When t < 0, v(0) = 0, i(0) = 0; for t > 0, 202.011,0 xLCo   = 0.25 + A cost + A sint = 10 + A cos(0.25t) + A sin(0.25t) i(t) = is 1 2 1 2 i(0) = 0 = 10 + A , therefore A = –10 1 1 Ldi(0)/dt = v(0) = 0 But di/dt = –A 0.25sin(0.25t) + A 0.25cos(0.25t) 1 2 leading to i(t) = 10(1 – cos(0.25t)) A At t = 0, di(0)/dt = 0 = 0 + 0.25A2 v(t) = Ldi/dt = 20x10x0.25sint = 50sin(0.25t) V –P.P.8.9 At t = 0, the switch is open so that v(0) = 0, i(0 ) = 0 (1) For t > 0, the switch is closed. We have the equivalent circuit as in Figure (a). i v(0+) = 0, i(0+) = 0 (2) –3 + iC + i = 0 (3) From (3), i(0+) = 0 means that iC(0 +) = 3, but iC(0 +) = Cdv(0+)/dt which leads to dv(0+)/dt = iC(0 +)/C = 3/(1/20) = 60 V/s As t approaches infinity, we have the equivalent circuit in (b). i() = 3 A, v() = 4i() = 12V (5) Next we find the network response by turning off the current source as shown in Figure (c). 10  (a) 3A 2 H (1/20)F 4  iC + v  10  (b) 3A i iC 4  10  (c) i 2 H (1/20)F iC 4  i + v  Thus, v2n = (Ae -t + Be-6t) and v2f = v2() = 20V. v2 = v2n + v2f = 20 + (Ae -t + Be-6t) v2(0) = 0 which implies that A + B = –20 (6) dv2/dt = (–Ae -t – 6Be-6t) dv2(0) = 0 = –A – 6B (7) From (6) and (7), A = –24 and B = 4. Thus, v2(t) = (20 – 24e -t + 4e-6t) V From (5), v1 = v2 + (1/3)dv2/dt Thus, v1(t) = (20 – 16e -t – 4e-6t) V Now we can find, vo = v1 – v2 = 8(e –t – e–6t) V, t > 0 P.P.8.11 Let v1 equal the voltage at non-inverting terminal of the op amp. Then vo is equal to the output of the op amp. At the non-inverting terminal, (vs – vo)/R1 = C1dv1/dt (1) At the output terminal of the op amp, (v1 – vo)/R2 = C2dvo/dt (2) We now eliminate v1 from (2), v1 = vo + R2C2dvo/dt (3) From (1) vs = v1 + R1C1dv1/dt (4) Substituting (3) into (4) gives vs = vo + R2C2dvo/dt + R1C1dvo/dt + R1C1R2C2d 2vo/dt 2 or d2vo/dt 2 + [(1/(R1C1)) + (1/(R2C2))]dvo/dt + vo/(R1R2C1C2) = vs/(R1R2C1C2) With the given parameters, (R1R2C1C2) = 10 4x104x20x10-6x100x10-6 = 2x10-2 1/(R1R2C1C2) = 5 [(1/(R1C1)) + (1/(R2C2))] = 10 -4[(1/20x10-6) + (1/200x10-6)] = 6 2Hence, we now have s + 6s + 5 = 0 = (s +1)(s + 5) -t -5t = Ae + Be , and v = 10V Therefore von of -t -5tThus, v = 10 + Ae + Be (5) o For t < 0, vs = 0, v1(0 –) = 0 = v (0–) o For t > 0, v = 10, but s v1(0 + +) – v (0 ) =0 (6) o From (2), dvo(0 +)/dt = [v1(0 +) – v (0+)]/R C = 0 (7) o 2 2 Imposing these conditions on v (t), o 0 = 10 + A + B (8) 0 = –A – 5B or A = –5B (9) From (8) and (9), A = –12.5 and B = 2.5 -t -5t(t) = (10 – 12.5e + 2.5e ) V, t > 0 vo P.P.8.12 We follow the same procedure as in Example 8.12. The schematic is shown in Figure (a). The current marker is inserted to display the inductor current. After simulating the circuit, the required inductor current is plotted in Figure (b). P.P.8.13 When the switch is at position a, the schematic is as shown in Figure (a). We carry out dc analysis on this to obtain initial conditions. It is evident that v (0) = 8 volts. C (a) With the switch in position b, the schematic is as shown in Figure (b). A voltage marker is inserted to display the capacitor voltage. When the schematic is saved and run, the output is as shown in Figure (c). 5  P.P.8.16 Since 12 = 4i + vL + vC or vC = 12 – 4i - vL –(vC – 12) = 4i + vL = e -250t(12cosdt + 0.2684sindt – 268sindt) vC(t) = [12 – 12e -250tcos(11,180t) + 267.7e-250tsin(11,180t)] V 3  (a) 4 H 0.2 H 4 F 0.2F 20 V +  2A 20A 2V +  0.2  1/3  1/3  4F 0.2 H 20A 0.2 + 2V  (b) P.P.8.17 We follow the same procedure as in Example 8.17. The schematic is as shown in Figure (a) with two voltage markers to display both input and output voltages. When the schematic is saved and run, the result is as displayed in Figure (b). (a) (a)